• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.3 s.333
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• pp.43-50
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• 2005

In this paper, quaternary logic gates using Down literal circuit(DLC) has been designed, and then synchronous Quaternary un/down counter using those gates has been proposed The proposed counter consists of T-type quaternary flip flop and 1-of-2 threshold-t MUX, and T-type quaternary flip flop consists of D-type quaternary flip flop and quaternary logic gates(modulo-4 addition gates, Quaternary inverter, identity cell, 1-of-4 MUX). The simulation result of this counter show delay time of 10[ns] and power consumption of 8.48[mW]. Also, assigning the designed counter to MVL(Multiple-valued Logic) circuit, it has advantages of the reduced interconnection and chip area as well as easy expansion of digit.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.11C
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• pp.649-654
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• 2011

In this paper, we show new method to find number of errors in the Reed-Solomon decoder. New design is much faster and has much simpler logic circuit than the former design method. This optimization was possible by very simplified square calculating circuit and parallel processing. The microcontroller of this Reed Solomon decoder can be used for data protection of almost all digital communication and consumer electronic devices.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.3B
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• pp.347-354
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• 2001

IEEE 1394 버스는 데이터 패킷 전송시 반이중(half duplex)으로, 0과 1의 두 상태를 이용하여 전송한다. 그러나 버스 자동 구성 및 중재 기간에서 양방향으로 버스 중재 선 상태(arbitrtation line state) 신호를 주고받으며, 이는 Z, 0. 1의 세 논리 상태를 가지고 있다. IEEE 1394 버스를 채택한 노드는 시스템에 연결시 자동으로 네트웍을 트리 구조로 구성하고, 6 비트 물리 ID를 할당하며, 이는 버스 리셋, 트리 식별, 자기 식별의 세과정을 통해 구성된다. 또 전송할 데이터가 있는 경우 노드는 버스의 사용권을 얻기 위한 버스 중재(arbitration) 후 전송을 시작한다. 이러한 시스템 자동 구성을 위한 과정들과 버스 중재 과정에서 양방향으로 아날로그 0, 1, Z의 중재 선 상태 신호를 주고받게 된다. 본 논문에서는 기존 IEEE 1394를 채택한 노드들과 화환되며 중재 선 상태를 0과 1의 논리 상태만을 사용하여 버스 자동 구성 및 버스 중재를 디지털 회로로 구성할 수 있는 중재 선 상태 디코딩 알고리즘을 제안하였고, VHDL을 이용하여 전체 시스템의 동작을 시뮬레이션하였다.

• Journal of the Korean Institute of Telematics and Electronics
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• v.18 no.5
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• pp.30-34
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• 1981

This paper deals with the testability evaluation method for the digital systems. This method uses two factors: the complexity and the accessibility. The complexity depends on the ratio in combinational and sequential circuits, number of input/output terminals, and the circuit count by using the gate input level method. The accessibility is how easily to handle the data from I/O terminals. The system testability has a normalized value. Thus, analyzing the testability evaluation, and redesigning the circuit to improve testability, the systems increase interests for the maintenance and have high reliability. Finally, in comparison with Stephenson and Grason's technique, this technique gives sufficiently accurate results for much less computation effort.

• Korean Journal of Optics and Photonics
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• v.8 no.6
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• pp.492-499
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• 1997

We proposed and studied an all-optical switching device made of a bent nonlinear waveguide and an all-optical logic gate made of a bent nonlinear Y-junction. The proposed devices as switch and a logic function are based on the evolution of nonlinear guided wave along a bent nonlinear waveguide. Since the characteristics of beam propagation depens on the nonlinearity, input power and bent angle of waveguide, the characteristics of output power transmission is calculated by variation the such parameters. Furthermore, by calculating the output power through the nonlinear media with different positions of detector in nonlinear media, we could find the ideal digital switching performance at specific position of detector and implement several all-optical logic functions (AND, OR, XOR) by power contrast between waveguide end and nonlinear media.

• Proceedings of the KIEE Conference
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• 2003.07d
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• pp.2717-2719
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• 2003

In this paper, we developed an efficient virtual experiment kit with creative and interactive multimedia contents, which can be used to enhance the quality of education in the area of digital logic circuits. Since our virtual experiment kit is implemented to describe the on-campus laboratory, the learners can obtain similar experimental data through it. Also, our web-based virtual experiment kit is designed to enhance the efficiency of both the learners and the educators. The learners will be able to achieve high learning standard and the educators save time and labor. The virtual experiment is performed according to the following procedure: (1) Circuit Composition on the Bread Board (2) Applying Input Voltage (3) Output Measurements (4) Checkout of Experiment Results. Furthermore, the circuit composition on the bread board and its corresponding online schematic diagram are displayed together on the virtual experiment kit for the learner's convenience. Finally, we have obtained several affirmative effects such as reducing the total experimental hours and the damage rate for experimental equipments and increasing learning efficiencies as well as faculty productivity.

• Journal of Korea Society of Industrial Information Systems
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• v.18 no.5
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• pp.59-65
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• 2013

Conventional synchronous design circuits cannot only satisfy the timing requirement of the low voltage digital systems, but also they may generate wrong outputs under the influence of PVT variations and aging effects. Therefore, in this paper, a NCL (Null Convention Logic) design as an asynchronous design method has been proposed, where the NCL method doesn't require any timing analysis, and it has a very simple design methodology. Base on the NCL method, a new low power reliable ALU has been designed and implemented using MagnaChip-SKhynix 0.18um CMOS technology. The experimental results of the proposed NCL ALU have been compared to those of a conventional pipelined ALU in terms of power consumption and speed.

• Journal of the Institute of Convergence Signal Processing
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• v.9 no.1
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• pp.54-61
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• 2008

This paper presents a new TIQ based CMOS flash 6-bit ADC to process digital signal in real time. In order to improve the conversion speed of ADC by designing new logic or layout of ADC circuits, a new design method is proposed in encoding logic circuits. The proposed encoding circuits convert analog input into digitally encoded double base number system(DBNS), which uses two bases unlike the normal binary representation scheme. The DBNS adopts binary and ternary radix to enhance digital arithmetic processing capability. In the DBNS, the addition and multiplication can be processed with just shift operations only. Finding near canonical representation is the most important work in general DBNS. But the main disadvantage of DBNS representation in ADC is the fan-in problem. Thus, an equal distribution algorithm is developed to solve the fan-in problem after assignment the prime numbers first. The conversion speed of simulation result was 1.6 GSPS, at 1.8V power with the Magna $0.18{\mu}m$ CMOS process, and the maximum power consumption was 38.71mW.

• Journal of Practical Engineering Education
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• v.10 no.1
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• pp.49-56
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• 2018

Various types of SW education are being operated by universities for non-major undergraduates. And most of them focus on educating computational thinking. Following this computing education, there is a need for an educational method that implements and evaluates creative computing outcomes for each student. In this paper, we propose a method to realize SW education based on creative computing artifacts. To do this, we propose an educational method for students to implement digital logic circuit devices creatively and design SW algorithms that implement the functions of their devices. The proposed training method teaches a simple LED logic circuit using an Arduino board as an example. Students creatively design and implement two pairs of two input logic circuit devices, and design algorithms that represent patterns of implemented devices in various forms. And they design the functional extension and extended algorithm using the input device. By applying the proposed method, non-major students can gain the concept and necessity of algorithm design through creative computing artifacts.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.24 no.4
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• pp.1-9
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• 2010

An LED driving and control circuit has been developed. The LED driver has a new PWM circuit for current control of LED columns with dimming, current and thermal control, and communication functions. The PWM circuit is composed of two ring oscillator and one counter which can be constructed using basic digital logic components. In addition, it has the functions of remote control mode such as ON, OFF, emergency and power saving modes by the serial communication. The PWM generator and control circuit have been designed and fabricated 0.35[${\mu}m$] Magnachip/Hynix digital IC fabrication process. The LED driving and control board using the developed chip is fabricated and tested successfully.