• Proceedings of the Korean Vacuum Society Conference
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• 2011.08a
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• pp.88-88
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• 2011

복합분자펌프는 기존의 터보분자펌프 turbine blade에 spiral grooved를 추가하여 초고진공(10-8 Pa)에서 저진공(330Pa)까지 넓은 압력범위에서 사용할 수 있고 이 펌프를 사용함으로서 완전 oil free한 진공시스템을 만들 수 있는 특징을 가지고 있다. 특히, 회전체를 비접촉으로 지지하는 자기베어링 방식을 적용함으로써, 진동은 극히 작고 베어링수명은 길면서 중저진공에 대한 배기속도가 크고 임의의 방향으로 접속이 가능하여 반도체 및 디스플레이 제조 공정과 같은 첨단산업의 다양한 분야에 쉽게 적용되고 있으며, 그 적용 분야와 시장은 계속 성장하고 있다. 고 진공과 배기 속도의 달성을 위해서, 고속으로 이동하는 격면과 기체분자를 충돌시켜, 기체 분자를 원하는 방향으로 유도하는 작동원리를 가지고 있다. 특히 공기분자의 밀도가 매우 낮은 희박가스 상태에서 고속 회전하는 blade로 공기분자를 쳐 내면서 작동됨으로써 날개의 상하 압력차에 의한 공기력보다도 날개의 고속회전이 매우 중요시 되고 압력으로는 10-1 Pa 이하의 분자영역에서 그 성능을 최고로 발휘 할 수 있다. 이러한 복합 펌프의 주요 장점은 다음과 같다. 1. 10-8 Pa (10-10torr)~10 Pa (1 torr) 까지 넓은 영역에서 배기가 가능하다. 2. 탄화수계의 대하여 높은 압축특성을 가지고 있고, 윤활유를 사용하지 않으므로 얻을 수 있는 진공상태가 고청정하다(oil free). 3. 정밀 5축제어 자기베어링으로 완전히 부상하여 회전함으로서 마모가 없고 진동이 최소화하였을 뿐만 아니라, 또한 운전음도 거의 없다. 4. 설치조건에 제한이 없고 고장이 거의 없다. 본 논문에서는 이러한 복합분자펌프의 개발을 위하여, 상기 연구기관에서 수행된 내용을 소개하고 있으며, 펌프 시스템의 기본 설계 및 자기베어링 시스템의 설계 결과 및 수치해석 결과를 나타내었다.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.4
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• pp.718-725
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• 2016

In this study, the plastic flow curve of commercially pure titanium sheet (CP Ti) actively used in the plate heat exchanger etc., was evaluated. The plastic flow curve known as hardening curve is a key factor needed in conducting finite element analyses (FEA) for the forming process of a sheet material. A hydraulic bulge test was performed on the CP Ti sheet and the strain in this test was measured using the DIC method and ARAMIS system. The measured true stress-true strain curve from the hydraulic bulge test (HBT) was compared with that from the tensile test. The measured true stress-true strain curve from the hydraulic bulge test showed stable plastic flow curve over the strain range of 0.7 which cannot be obtained in the case of the uniaxial tensile test. The measured true stress-true strain curve from the hydraulic bulge test can be fitted well by the hardening equation known as the Kim-Tuan model.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.40 no.7
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• pp.1347-1353
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• 2015

We implemented a 10 Gb/s 4-channel vertical cavity surface emission lasers (VCSEL) driver array in a $0.13{\mu}m$ CMOS process technology. To enhance high current resolution, power dissipation, and chip space area, digital APC/AMC with time division sensing technology is primarily adopted. The measured -3 dB frequency bandwidth is 9.2 GHz; the small signal gain is 10.5 dB; the current resolution is 0.01 mA/step, suitable for the wavelength operation up to 10 Gb/s over a wide temperature range. The proposed APC and AMC demonstrate 5 to 20 mA of bias current control and 5 to 20 mA of modulation current control. The whole chip consumes 371 mW of low power under the maximum modulation and bias currents. The active chip size is $3.71{\times}1.3mm^2$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.12
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• pp.52-57
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• 2011

This paper presents a 4-channel optical transmitter circuit realized in a $0.18{\mu}m$ CMOS technology for high-speed digital interface. Particularly, the VCSEL driver exploits the feed-forward technique, and the pre-amplifier employs the pulse-width control. Thus, the optical transmitter operates at the bias current up to 4mA and the modulation current from $2{\sim}8mA_{pp}$. with the pulse-width distortion compensated effectively. The 4-channel optical transmitter array chip occupies the area of $1.0{\times}1.7mm^2$ and dissipates 35mW per channel at maximum current operations from a single 1.8V supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.6
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• pp.35-40
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• 2012

This paper has proposed a 3~5 GHz IR-UWB low power transmitter for range detection application. Proposed transmitter which has been implemented in a $0.13{\mu}m$ CMOS technology is all digital circuit that consist of simple digital logic. this feature insure low complexity and low power consumption. In addition, center frequency can be changed by adopting voltage controlled delay cell for avoiding existing another radio frequency in UWB low band. Proposed circuit consume only 10pJ/b from 1.2 V supply voltage. The simulation results show 3.3~4.3 GHz center frequency controllability, -51 dBm/MHz maximum output power and is satisfied with FCC regulation.

• The Journal of the Korea institute of electronic communication sciences
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• v.12 no.2
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• pp.273-280
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• 2017

As massive integration technology of transistors has been developing, multi-core circuit is fabricated on a silicon chip and a clock frequency is getting faster to meet the system requirement. But increasing the clock frequency can induce some problems to violate the operation of system such as clock synchronization, so it is very import to avoid metastability events to design digital chips. In this paper, metastability windows are measured by bisection method in H-spice depending on temperature, supply voltage, and the size of transmission gate with D-FF designed with 180nm CMOS process. The simulation results show that the metastability window(: MW) is slightly increasing to temperature and supply voltage, but is quadratic to the area of a transmission gate, and the best area ration of P and Ntransitor in transmission gate is P/N=4/2 to get the least MW.

• Journal of IKEEE
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• v.18 no.2
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• pp.263-271
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• 2014

This paper presents design of the second-order sigma-delta modulator for converting voltage and temperature signals to digital ones in Battery Management IC (BMIC) for mobile applications. The second-order single-loop switched-capacitor sigma-delta modulator with 1-bit quantization in 0.13-um CMOS technology is proposed. The proposed modulator is designed using switched-opamp technique for saving power consumption. With an oversampling ratio of 256 and clock frequency of 256kHz, the modulator achieves a measured 83-dB dynamic range and a peak signal-to-(noise+distortion) ratio (SNDR) of 81.7dB. Power dissipation is about 0.66 mW at 3.3 V power supply and the occupied core area is $0.425mm^2$.

• Journal of IKEEE
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• v.24 no.1
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• pp.319-325
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• 2020

In this paper, a discontinuous-conduction mode (DCM) DC-DC buck converter is presented for mobile device applications. The buck converter consists of compensator for stable operations, pulse-width modulation (PWM) logic, and power switches. In order to achieve small hardware form-factor, the number of off-chip components should be kept to be minimum, which can be realized with simple and efficient frequency compensation and digital soft start-up circuits. Burst-mode operation is included for preventing the efficiency from degrading under very light load condition. The DCM DC-DC buck converter is fabricated with 0.18-um BCDMOS process. Programmable output with external resistors is typically set to be 1.8V for the input voltage between 2.8 and 5.0V. With a switching frequency of 1MHz, measured maximum efficiency is 92.6% for a load current of 100mA.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.1A
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• pp.104-112
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• 2005

Some design techniques for high speed and low power pipelined 8-bit ADC are described. To perform high-speed operation with relatively low power consumption, open loop architecture is adopted, while closed loop architecture (with MDAC) is used in conventional pipeline ADC. A distributed track and hold amplifier and a cascading structure are also adopted to increase the sampling rate. To reduce the power consumption and the die area, the number of amplifiers in each stage are optimized and reduced with proposed zero-crossing point generation method. At 500-MHz sampling rate, simulation results show that the power consumption is 210mW including digital logic with 1.8V power supply. And the targeted ADC achieves ENOB of about 8-bit with input frequency up to 200-MHz and input range of 1.2Vpp (Differential). The ADC is designed using a $0.18{\mu}m$ 6-Metal 1-Poly CMOS process and occupies an area of $900{\mu}m{\times}500{\mu}m$

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39C no.1
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• pp.82-89
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• 2014

Recently, inertial sensors are popularly used for the location and position recognition of small devices for M2M/IoT. In this paper, we designed low power, low noise, small sized 6-axis inertial sensor IC for mobile applications, which uses a 3-axis piezo-electric gyroscope sensor and a 3-axis piezo-resistive accelerometer sensor. Proposed IC is composed of 3-axis gyroscope readout circuit, two gyroscope sensor driving circuits, 3-axis accelerometer readout circuit, 16bit sigma-delta ADC, digital filter and control circuit and memory. TSMC $0.18{\mu}m$ mixed signal CMOS process was used. Proposed IC reduces 27% of the current consumption of LSM330.