• The Transactions of the Korean Institute of Power Electronics
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• v.4 no.1
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• pp.26-34
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• 1999

According to increase of nonlinear power electronics equipment, active power filters have been researched and developed for many years to compensate harmonic disturbances and reactive power. However the commercial of active power filter is being proceeded slowly, because the cost of active power filter compared to the passive filter for harmonic and reactive power compensation is expensive. Especially, the use of DSP (Digital Signal Processing) chip, which is frequently used to control 3-phase active power filter, is a factor of increasing the cost of active power filters. On the other hand, the use of only analog controller makes the controller's circuits much more complicate and depreciates the flexibilities of controller. In this paper, a controller with low cost for 5[kVA] 3-phase active power filter system is designed. To reduce the expense of active filter system, the presented controller is composed of digital control part using Intel 80C196KC $\mu$P and analog control part using hysteresis controller for current control. Characteristic analysis of designed controller for active filter system is performed by computer simulation and compensating characteristics of the designed controller are verified by experiment.tegy can apply to the vector control, leading to better output torque capability in the ac motor drive system. This strategy is that in the overmodulation range, the d-axis output current is given a priority to regulate the flux well, instead the q-axis output curent is sacrificed. Therefore, the vector control even in the overmodulation PWM operation can be achieved well. For this purpose, the d-axis output voltage of a current controller to control the flux is conserved. the q-axis output voltage to control the torque is controlled to place the reference voltage vector on the hexagon boundary in case of the overmodulation. The validity of the proposed overall scheme is confirmed by simulation and experiments for a 22[kW] induction motor drive system.

• The Journal of the Acoustical Society of Korea
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• v.24 no.1
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• pp.11-20
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• 2005

In this paper, we deal with the research about a S/PDIF (Sony Philips Digital Interface) receiver which can operate without PLL (Phase Locked Loop) circuits. Although a S/PDIF receiver is used in most audio devices and audio processors in these days. yet there are only few domestic researches about S/PDIF. Currently used commercial DACs (Digital-to-Analog Converters) which can decode S/PDIF signals, have a PLL circuit inside them. The PLL makes it possible to extract clock information from S/PDIF digital signal and to synchronize a clock signal with input signals. But the PLL circuit makes many diffculties in designing the SOC (System On Chips) of VLSIs (Vew Large Scale Integrated Ciruits) because it is an "analog circuit". We proposed a S/PDIF receiver which doesn't have PLL circuits and only has Pure digital circuits. The key idea of the proposed S/PDIF receiver. is to use the ratio between a 16 MHz basic input clock and S/PDIF signals. After having decoded hundreds thousands S/PDIF inputs, it went to prove that a S/PDIF receiver can be designed with pure digital circuits and without any analog circuits such as PLL circuits. We have confidence that the proposed S/PDIF receiver can be used as an IP (Intellectual Property) for the SOC design of the digital circuits.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.3
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• pp.96-101
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• 2015

This paper describes a design and implementation of the NFC bridge chip which performs interface between kinds of devices and mobile phones including NFC controller through NFC communication. The NFC bridge chip consists of the digital part and the analog part which are based on NFC Forum standard. Therefore the chip treats RF signals and then transforms the signal to digital data, so it can interface kinds of devices with the digital data. Especially the chip is able to detect RF signals and then wake up the host processor of a device. The wakeup function dramatically decreases the power consumption of the device. The carrier frequency is 13.56MHz, and the data rate is up to 424kbps. The chip has been fabricated with SMIC 180nm mixed-mode technology. Additionally an NFC bridge chip application to the blood glucose measurement system is described for an application example.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.9
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• pp.14-23
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• 2010

This paper reports the fabrication of a DVB-T/H System in Package (SiP) that is able to receive and process the DVB-T/H signal. The DVB-T/H is the European telecommunication standard for Digital Video Broadcasting (DVB). An IC-embedded Printed Circuit Board (PCB) process, interpose a chip between PCB layers, has applied to the DVB-T/H SiP. The chip inserted in DVB-T/H SiP is the System on Chip (SoC) for mobile TV. It is comprised of a RF block for DVB-T/H RF signal and a digital block to convert received signal to digital signal for an application processor. To operate the DVB-T/H IC, a 3MHz DC-DC converter and LDO are on the DVB-T/H SiP. And a 38.4MHz crystal is used as a clock source. The fabricated DVB-T/H SiP form 4 layers which size is $8mm{\times}8mm$. The DVB-T/H IC is located between 2nd and 3rd layer. According to the result of simulation, the RF signal sensitivity is improved since the layout modification of the ground plane and via. And we confirmed the adjustment of LC value on power transmission is necessary to turn down the noise level in a SiP. Although the size of a DVB-T/H SiP is decreased over 70% than reference module, the power consumption and efficiency is on a par with reference module. The average power consumption is 297mW and the efficiency is 87%. But, the RF signal sensitivity is declined by average 3.8dB. This is caused by the decrease of the RF signal sensitivity which is 2.8dB, because of the noise from the DC-DC converter.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.4
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• pp.659-666
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• 2006

Servo-motors are used as key components of automated system by performing precise motion control as accurate positioning and accurate speed regulation in response to the commands from computers and sensors. Especially, the linear brushless servo-motors have numerous advantages over the rotary servo motors which have connection with the friction induced transfer mechanism such as ball screws, timing belts, rack/pinion. This paper proposes an estimation method of unknown motor system parameters using the informations from the sinusoidal driving type linear brushless DC motor dynamics and outputs. The estimated parameters can be used to tune the controller gain and a disturbance observer. In order to meet this purpose high performance Digital Signal Processor, TMS320F240, designed originally for implementation of a Field Oriented Control(FOC) technology is adopted as a controller of the liner BLDC servo motor. Having A/D converters, PWM generators, rich I/O port internally, this servo motor application specific DSP play an important role in servo motor controller. This linear BLDC servo motor system also contains IPM(Intelligent Power Module) driver and hail sensor type current sensor module, photocoupler module for isolation of gate signals and fault signals.

• Journal of Biomedical Engineering Research
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• v.19 no.1
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• pp.59-68
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• 1998

Digital hearing aids offer many advantages over conventional analog hearing aids. With the advent of high speed digital signal processing chips, new digital techniques have been introduced to digital hearing aids. In addition, the evaluation of new ideas in hearing aids is necessarily accompanied by intensive subject-based clinical tests which requires much time and cost. In this paper, we present an objective method to evaluate and predict the performance of hearing aid systems without the help of such subject-based tests. In the hearing impairment simulation(HIS) algorithm, a sensorineural hearing impairment medel is established from auditory test data of the impaired subject being simulated. Also, the nonlinear behavior of the loudness recruitment is defined using hearing loss functions generated from the measurements. To transform the natural input sound into the impaired one, a frequency sampling filter is designed. The filter is continuously refreshed with the level-dependent frequency response function provided by the impairment model. To assess the performance, the HIS algorithm was implemented in real-time using a floating-point DSP. Signals processed with the real-time system were presented to normal subjects and their auditory data modified by the system was measured. The sensorineural hearing impairment was simulated and tested. The threshold of hearing and the speech discrimination tests exhibited the efficiency of the system in its use for the hearing impairment simulation. Using the HIS system we evaluated three typical hearing aid algorithms.

• The KIPS Transactions:PartA
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• v.13A no.4 s.101
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• pp.275-288
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• 2006

Rapid design space exploration is crucial to customizing embedded system design for exploiting the application behavior. As the time-to-market becomes a key concern of the design, the approach based on an application specific instruction-set processor (ASIP) is considered more seriously as one alternative design methodology. In this approach, the instruction set architecture (ISA) for a target processor is frequently modified to best fit the application with regard to code size and speed. Two goals of this paper is to introduce our new retargetable compiler and how it has been used in ASIP-based design space exploration for a popular digital signal processing (DSP) application. Newly developed retargetable compiler provides not only the functionality of previous retargetable compilers but also visualizes the features of the application program and profiles it so that it can help architecture designers and application programmers to insert new application specific instructions into target architecture for performance increase. Given an initial RISC-style ISA for the target processor, we characterized the application code and incrementally updated the ISA with more application specific instructions to give the compiler a better chance to optimize assembly code for the application. We get 32% performance increase and 20% program size reduction using 6 audio codec specific instructions from retargetable compiler. Our experimental results manifest a glimpse of evidence that a higgly retargetable compiler is essential to rapidly prototype a new ASIP for a specific application.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.39 no.3
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• pp.1-7
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• 2002

This paper presents a new PLL clock generator that can improve a jitter noise characteristics and acquisition process by designing a multi-PFD(Phase Frequency Detector) and an adaptive charge pump circuit. The conventional PLL has not only a jitter noise caused from such a demerit of the wide dead zone and duty cycle, but also a long delay interval that makes a high speed operation unable. An advanced multi-structured PFD circuit using the TSPC(True Single Phase Clocking) circuit is proposed, in which it shows an excellent functionalities in terms of the jitter noises by designing its circuit with the exact dead zone and duty cycle. Our new designed adaptive charge pump in the loop filter of a PLL can improve an acquisition characteristic by adaptively increasing of current. The Hspice simulation is done to evaluate the performance of the proposed circuit. Simulation result shows that our PLL has under 0.01ns in the dead zone, no influence from the duty cycle of input signals and under 50ns in the acquisition time. This circuit will be able to be used in develops of high-performance microprocessors and digital systems.  

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.2 s.344
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• pp.66-75
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• 2006

This paper addresses the implementation of FTTH system based on Ethernet PON technololy. This system consists of OLT and ONT. OLT supports the maximum 24 Gigabit Ethernet interfaces, and then has the flexibility and the scalability for supplying digital communication and broadcasting convergence service in the near future. OLT system consists of switch module, subscriber module, processor module, and E-PON link module, and has the operating system based on Linux. ONT is installed in customer premise to supply both IP-TV and Internet service. Also ONT has the dedicated interface for IP-TV to improve the transmission characteristics of IP-TV signal. We measure the performance of E-PON MAC through this system and then QoS control characteristics per franc in ONT by separating the virtual link for IP-TV from that for data.

• Journal of Broadcast Engineering
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• v.12 no.1 s.34
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• pp.53-60
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• 2007

A Digital Broadcasting Satellite (DBS) receiver converts digital A/V streams received from a satellite to analog NTSC A/V signals in real-time. Multi-tasking is an efficient way to improve the utilization of the processor core in real-time applications. In this paper, we propose a hybrid approach with a balanced trade-off between hardware kernel and multi-tasking programming to increase a system throughput. First, the schedulability of the critical hard real-time tasks in the DBS receiver is verified by using a simple feasibility test. Then, several soft real-time tasks are thoughtfully programmed to satisfy functional requirements of the system.