• The Transactions of The Korean Institute of Electrical Engineers
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• v.57 no.3
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• pp.421-428
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• 2008

The DVS(Dynamic Voltage Scaling) technique is the method to reduce the dynamic energy consumption. As using slack times, it extends the execution time of the big load operations by changing the frequency and the voltage of variable voltage processors. Researches, that controlling the energy consumption of the processors and the data transmission among processors by controlling the bandwidth to reduce the energy consumption of the entire system, have been going on. Since operations in multiprocessor systems have the data dependency between processors, however, the DVS techniques devised for single processors are not suitable to improve the energy efficiency of multiprocessor systems. We propose the new scheduling algorithm based on DVS for increasing energy efficiency of multiprocessor systems. The proposed DVS algorithm can improve the energy efficiency of the entire system because it controls frequency and voltages having the data dependency among processors.

• Proceedings of the KIEE Conference
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• 1992.07a
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• pp.354-358
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• 1992

본 연구에서는 n-차 비선형 로보트 매니퓰레이터에서 링크의 동특성에 액류웨이터의 동특성을 포함시킨 복합모델(Combined Model)의 알고리즘을 제안하였다. 여기서 이 복합 모델의 알고리즘은 고속운전 및 빈번한 부하의 변동시에 중요한 역할을 하는 액류웨이터 모터의 동특성 방정식과 매니퓰레이터 링크의 운동을 묘사하는 동특성 방정식을 포함시킨 알고리즘을 의미한다. 또한 제안된 모델은 선영궤환 및 감결합 변환(Feedback Linearizing and Decoupling Transformation : FLDT)법을 이용하여 선형시스템으로 변환시켰다. 따라서 본 연구에서는 고속운전 및 빈번한 부하의 변동에도 액류웨이터 모터의 전압과 전류를 조절함으로써 효과적으로 제어할 수 있게 하는 매니퓰레이터 모델 알고리즘을 개발하는데 그 목적이 있다.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.21 no.6
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• pp.71-76
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• 2021

Recently, as the size of IoT data grows, the memory power consumption of real-time systems increases rapidly. This is because real-time systems always place entire tasks in memory, which increases the demand of DRAM significantly. In this paper, we adopt emerging fast storage media and move a certain portion of real-time tasks from DRAM to storage. The part of tasks in storage are, then, loaded into memory when they are actually used. We incorporate our memory/storage power-saving into the dynamic voltage/frequency scaling of processors, thereby optimizing power consumptions in CPU and memory simultaneously. Specifically, the proposed technique aims at minimizing the CPU idle time and the DRAM memory size by determining appropriate voltage modes of CPU and the swap ratio of memory, without violating the deadlines of all tasks. Through simulation experiments, we show that the proposed technique significantly reduces the power consumption of real-time systems.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.3 s.345
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• pp.21-32
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• 2006

A new SRAM circuit with row-by-row activation and low-swing write schemes is proposed to reduce switching power of active cells as well as leakage one of sleep cells in this paper. By driving source line of sleep cells by $V_{SSH}$ which is higher than $V_{SS}$, the leakage current can be reduced to 1/100 due to the cooperation of the reverse body-bias. Drain Induced Barrier Lowering (DIBL), and negative $V_{GS}$ effects. Moreover, the bit line leakage which may introduce a fault during the read operation can be eliminated in this new SRAM. Swing voltage on highly capacitive bit lines is reduced to $V_{DD}-to-V_{SSH}$ from the conventional $V_{DD}-to-V_{SS}$ during the write operation, greatly saving the bit line switching power. Combining the row-by-row activation scheme with the low-swing write does not require the additional area penalty. By the SPICE simulation with the Berkeley Predictive Technology Modes, 93% of leakage power and 43% of switching one are estimated to be saved in future leakage-dominant 70-un process. A test chip has been fabricated using $0.35-{\mu}m$ CMOS process to verify the effectiveness and feasibility of the new SRAM, where the switching power is measured to be 30% less than the conventional SRAM when the I/O bit width is only 8. The stored data is confirmed to be retained without loss until the retention voltage is reduced to 1.1V which is mainly due to the metal shield. The switching power will be expected to be more significant with increasing the I/O bit width.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.20 no.1
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• pp.135-140
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• 2020

Recently, due to the rapid diffusion of intelligent systems and IoT technologies, power saving techniques in real-time embedded systems has become important. In this paper, we propose P-GA (Parallel Genetic Algorithm), a scheduling algorithm aims at reducing the power consumption of real-time systems in multi-core hybrid memory environments. P-GA improves the Proportional-Fairness (PF) algorithm devised for multi-core environments by combining the dynamic voltage/frequency scaling of the processor with the nonvolatile memory technologies. Specifically, P-GA applies genetic algorithms for optimizing the voltage and frequency modes of processors and the memory types, thereby minimizing the power consumptions of the task set. Simulation experiments show that the power consumption of P-GA is reduced by 2.85 times compared to the conventional schemes.

• KIPS Transactions on Computer and Communication Systems
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• v.2 no.6
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• pp.237-244
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• 2013

We propose Energy-constrained Multiprocessor Real-Time Scheduling algorithms for (m,k)-firm deadline constrained tasks (EMRTS-MK). Rather than simply saving as much energy as possible, we consider energy as hard constraint under which the system remains functional and delivers an acceptable performance at least during the prescribed mission time. We evaluate EMRTS-MKs in several experiments, which quantitatively show that they achieve the scheduling objectives.

• Journal of Korea Multimedia Society
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• v.13 no.10
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• pp.1423-1435
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• 2010

Building wireless sensor networks requires a constituting sensor node to consider the following limited hardware resources: a small battery lifetime limiting available power supply for the sensor node, a low-power microprocessor with a low-performance computing capability, and scarce memory resources. Despite such limited hardware resources of the sensor node, the sensor node platform needs to activate real-time sensing, guarantee the real-time processing of sensing data, and exchange data between individual sensor nodes concurrently. Therefore, in this paper, we propose an energy-efficient real-time task scheduling technique for battery-powered wireless sensor nodes. The proposed energy-efficient task scheduling technique controls the microprocessor's operating frequency and reduces the power consumption of a task by exploiting the slack time of the task when the actual execution time of the task can be less than its worst case execution time. The outcomes from experiments showed that the proposed scheduling technique yielded efficient performance in terms of guaranteeing the completion of real-time tasks within their deadlines and aiming to provide low power consumption.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.23 no.5
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• pp.109-114
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• 2023

In this paper, a 2-channel Image-Reject receiver using a 65-nm CMOS process is presented for Ka-band compact radars. The designed receiver consists of Low-Noise Amplifier (LNA), IQ mixer, and Analog Baseband (ABB). ABB includes a complex filter in order to suppress unwanted images, and the variable gain amplifiers (VGAs) in RF block and ABB have gain tuning range from 4.5-56 dB for wide dynamic range. The gain of the receiver is controlled by on-chip SPI controllers. The receiver has noise figure of <15 dB, OP1dB of >4 dBm, image rejection ratio of >30 dB, and channel isolation of >45 dB at the voltage gain of 36 dB, in the Ka-band target frequency. The receiver consumes 420 mA at 1.2 V supply with die area of 4000×1600 ㎛.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.5
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• pp.25-33
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• 2011

This work proposes a skinny-type 10b 50MS/s 0.13um CMOS three-step pipeline ADC for CIS applications. Analog circuits for CIS applications commonly employ a high supply voltage to acquire a sufficiently acceptable dynamic range, while digital circuits use a low supply voltage to minimize power consumption. The proposed ADC converts analog signals in a wide-swing range to low voltage-based digital data using both of the two supply voltages. An op-amp sharing technique employed in residue amplifiers properly controls currents depending on the amplification mode of each pipeline stage, optimizes the performance of op-amps, and improves the power efficiency. In three FLASH ADCs, the number of input stages are reduced in half by the interpolation technique while each comparator consists of only a latch with low kick-back noise based on pull-down switches to separate the input nodes and output nodes. Reference circuits achieve a required settling time only with on-chip low-power drivers and digital correction logic has two kinds of level shifter depending on signal-voltage levels to be processed. The prototype ADC in a 0.13um CMOS to support 0.35um thick-gate-oxide transistors demonstrates the measured DNL and INL within 0.42LSB and 1.19LSB, respectively. The ADC shows a maximum SNDR of 55.4dB and a maximum SFDR of 68.7dB at 50MS/s, respectively. The ADC with an active die area of 0.53$mm^2$ consumes 15.6mW at 50MS/s with an analog voltage of 2.0V and two digital voltages of 2.8V ($=D_H$) and 1.2V ($=D_L$).

• Journal of the Korea Society of Computer and Information
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• v.14 no.1
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• pp.145-151
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• 2009

There are excessively hot units of a microprocessor in today's nano-scale process technology, which are called hotspots. Hotspots' heat dissipation is not perfectly conquered by mechanical cooling techniques such as heatsink, heat spreader, and fans; Hence, an architecture-level temperature simulation of microprocessors is evident experiment so that designers can make reliable chips in high temperature environments. However, conventional thermal simulators cannot be used in temperature evaluation of real machine, since they are too slow, or too coarse-grained to estimate overall system models. This paper proposes methodology of monitoring accurate runtime temperature with Hotspot[4], and introduces its implementation. With this tool, it is available to track runtime thermal behavior of a microprocessor at architecture-level. Therefore, Dynamic Thermal Management such as Dynamic Voltage and Frequency Scaling technique can be verified in the real system.