• Journal of KIISE:Computing Practices and Letters
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• v.16 no.2
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• pp.212-216
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• 2010

Dynamic Thermal Management (DTM) degrades the processor performance for lowering temperature. For this reason, reducing the peak temperature on microprocessors can improve the performance by reducing the performance loss due to DTM. In this study, we analyze various unit selection techniques for computation migration. According to our simulation results, dynamic computation migration based on the thermal difference between the units shows best performance among compared models.

• Proceedings of the KIPE Conference
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• 2018.11a
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• pp.213-214
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• 2018

본 논문에서는 전기자동차 온-보드 충전기용 단상 cycloconverter-type high frequency link 컨버터의 전력 제어성능과 동적 응답특성을 개선하기 위하여 예측전류제어 기법을 적용한다. 배터리를 충전 및 방전하기 위하여 전력계통에 연결되는 V2G 충전기는 전압 변동, 고조파 왜곡 등의 외란 발생에도 강인한 동적 응답 특성을 유지하여야 한다. 예측전류제어 기법이 적용된 제어기는 계통 외란이 존재하는 경우에도 전력 레퍼런스를 빠르게 추적하고 정확한 듀티를 생성할 수 있으므로 우수한 동적 및 과도 응답특성을 갖는다. 제안하는 제어기의 성능과 파라미터 변동에 대한 민감도는 PSIM 시뮬레이션을 이용하여 평가되며, 여러 계통외란 상태에서 PI 제어기와 비교된다.

• The KIPS Transactions:PartA
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• v.19A no.2
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• pp.77-84
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• 2012

Speculative execution for improving instruction-level parallelism is widely used in high-performance processors. In the speculative execution technique, the most important factor is the accuracy of branch predictor. Unfortunately, complex branch predictors for improving the accuracy can cause serious thermal problems in 3D multicore processors. Thermal problems have negative impact on the processor performance. This paper analyzes two methods to solve the thermal problems in the branch predictor of 3D multi-core processors. First method is dynamic thermal management which turns off the execution of the branch predictor when the temperature of the branch predictor exceeds the threshold. Second method is thermal-aware branch predictor placement policy by considering each layer's temperature in 3D multi-core processors. According to our evaluation, the branch predictor placement policy shows that average temperature is $87.69^{\circ}C$, and average maximum temperature gradient is $11.17^{\circ}C$. And, dynamic thermal management shows that average temperature is $89.64^{\circ}C$ and average maximum temperature gradient is $17.62^{\circ}C$. Proposed branch predictor placement policy has superior thermal efficiency than the dynamic thermal management. In the perspective of performance, the proposed branch predictor placement policy degrades the performance by 3.61%, while the dynamic thermal management degrades the performance by 27.66%.

• Proceedings of the Korean Information Science Society Conference
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• 2010.06b
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• pp.313-317
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• 2010

최근에는 반도체 공정 기술의 발달로 인하여 프로세서의 성능은 급속도록 발전하였다. 하지만 프로세서에서 소모되는 전력이 급속도록 증가하고, 이에 따라 발생된 높은 온도는 프로세서 신뢰성에 부정적인 영향을 미치고 있다. 그러므로 최근의 프로세서 설계 시 전력, 온도등도 성능과 함께 중요한 고려사항이다. 프로세서의 신뢰성에 치명적인 영향을 미치는 고온현상을 해결하기 위해서 여러 가지 연구가 이루어지고 있다. 대표적으로 방열 판, 냉각 팬 등을 이용한 기계적인 기법과 동적 온도 관리 기법, 연산 이관 기법등을 적용한 구조적인 기법이 활발하게 연구되고 있다. 이러한 기법들의 적용으로 프로세서의 온도를 효과적으로 제어할 수 있게 되었으나 기계적인 냉각 기법은 냉각 효율성이 높지 않다는 단점이 존재하고, 구조적 설계 기법을 통한 냉각기법은 온도를 제어하기 위해 프로세서의 성능을 저하시키는 치명적인 단점이 존재하기 때문에 두 기법 모두 더 많은 연구가 필요하다. 최근의 프로세서 온도 제어 연구의 초점은 부가적인 장치를 통해 프로세서 내에서 발생 된 온도를 제어하는 기계적인 냉각 기법에서 프로세서 내에서 발생하는 온도를 효과적으로 제어하여 프로세서의 신뢰성과 냉각 비용을 절감할 수 있는 구조적 설계 기법으로 이동하고 있다. 본 논문에서는 연구의 초점이 이동하는 원인에 대해 분석하고자 고성능 프로세서에서의 기계적 냉각 기법의 냉각 효율성을 분석하고자 한다. 실험 결과, 온도를 제어하는 데 있어서 매우 높은 비용($1^{\circ}C$ 감소 당 최대 3.58W, 평균 3.36W)이 소모되는 것으로 나타났다. 향후에는 구조적인 설계 기법의 냉각 효율성을 분석하는 실험을 진행하고자 한다.

• Journal of KIISE:Computer Systems and Theory
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• v.35 no.12
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• pp.540-551
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• 2008

Today's microprocessor designs are not free from temperature as well as power consumption. As processor technology scales down, an on-chip circuitry increases power density, which incurs excessive temperature (hotspot) problem. To tackle thermal problems cost-effectively, Dynamic Thermal Management (DTM) has been suggested: DTM techniques have benefits of thermal reliability and cooling cost. However, they require trade-off between thermal control and performance loss. This paper proposes a dual integer register file structure to minimize the performance degradation due to DTM invocations. In on-chip thermal control, the most important functional unit is an integer register file. It is the hotspot unit because of frequent read and write data accesses. The proposed dual integer register file migrates read data accesses by adding an extra register file, thus reduces per-unit dynamic power dissipation. As a result, the proposed structure completely eliminates localized hotspots in the integer register file, resulting in much less performance degradation by average 13.35% (maximum 18%) improvement compared to the conventional DTM architecture.

• Journal of the Korea Society of Computer and Information
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• v.20 no.2
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• pp.71-77
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• 2015

This paper suggested dynamic application framework based data collecting and monitoring technique using wireless sensor network. The development of application for wireless measurement node firmware program integrates with various sensors and performs control. Collecting data of the user application is downloaded from the node onboard process wirelessly. In addition, the user application can change the temperature initial value of the nodes, which enables dynamic sampling of the measurement nodes. Therefore, dynamic sampling control of the nodes can reduce the power consumptions of sensors compared to existing wired data monitoring.

• Journal of KIISE:Computer Systems and Theory
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• v.36 no.6
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• pp.532-542
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• 2009

Dynamic Thermal Management (DTM) technique is generally used for reducing the peak temperature (hotspot) in the microprocessors. Despite the advantages of lower cooling cost and improved stability, the DTM technique inevitably suffers from performance loss. This paper proposes the DualFloating-Point Adders Architecture to minimize the performance loss due to thermal problem when the floating-point applications are executed. During running floating-point applications, only one of two floating-point adders is used selectively in the proposed architecture, leading to reduced peak temperature in the processor. We also propose a new floorplan technique, which creates Space for Heat Transfer Delay in the processor for solving the thermal problem due to heat transfer between adjacent hot units. As a result, the peak temperature drops by $5.3^{\circ}C$ on the average (maximum $10.8^{\circ}C$ for the processor where the DTM is adopted, consequently giving a solution to the thermal problem. Moreover, the processor performance is improved by 41% on the average by reducing the stall time due to the DTM.

• The KIPS Transactions:PartA
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• v.17A no.6
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• pp.265-274
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• 2010

As the process technology scales down and integration densities continue to increase, interconnection has become one of the most important factors in performance of recent multi-core processors. Recently, to reduce the delay due to interconnection, 3D architecture has been adopted in designing multi-core processors. In 3D multi-core processors, multiple cores are stacked vertically and each core on different layers are connected by direct vertical TSVs(through-silicon vias). Compared to 2D multi-core architecture, 3D multi-core architecture reduces wire length significantly, leading to decreased interconnection delay and lower power consumption. Despite the benefits mentioned above, 3D design technique cannot be practical without proper solutions for hotspots due to high temperature. In this paper, we propose three floorplan schemes for reducing the peak temperature in 3D multi-core processors. According to our simulation results, the proposed floorplan schemes are expected to mitigate the thermal problems of 3D multi-core processors efficiently, resulting in improved reliability. Moreover, processor performance improves by reducing the performance degradation due to DTM techniques. Power consumption also can be reduced by decreased temperature and reduced execution time.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.34 no.8
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• pp.981-987
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• 2010

The split Hopkinson pressure bar (SHPB) technique is extensively used to characterize material deformation behavior under high strain rate condition. In this study, the dynamic deformation behavior of aluminum 7075-T6 under a high strain rate and at a high temperature is investigated by using a modified SHPB set-up with the pulse shaper technique. The parameters used in the Johnson-Cook constitutive equation are determined by using the SHPB experimental results including the data on the effects of strain rate, temperature, strain hardening, and thermal softening of the material.

• Journal of the Korea Society of Computer and Information
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• v.14 no.1
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• pp.145-151
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• 2009

There are excessively hot units of a microprocessor in today's nano-scale process technology, which are called hotspots. Hotspots' heat dissipation is not perfectly conquered by mechanical cooling techniques such as heatsink, heat spreader, and fans; Hence, an architecture-level temperature simulation of microprocessors is evident experiment so that designers can make reliable chips in high temperature environments. However, conventional thermal simulators cannot be used in temperature evaluation of real machine, since they are too slow, or too coarse-grained to estimate overall system models. This paper proposes methodology of monitoring accurate runtime temperature with Hotspot[4], and introduces its implementation. With this tool, it is available to track runtime thermal behavior of a microprocessor at architecture-level. Therefore, Dynamic Thermal Management such as Dynamic Voltage and Frequency Scaling technique can be verified in the real system.