• Proceedings of the Korea Information Processing Society Conference
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• 2005.05a
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• pp.731-734
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• 2005

학술지 정보는 다른 문헌 정보와는 달리 시간에 따라 지속적으로 변화하는 동적인 특성, 형태나 소장정보의 다양성, 정보 제공에 시한성 등이 있기 때문에 학술지 정보 데이터베이스의 자동구축과 실시간 갱신 등이 절대적으로 요구되고 있다. 학술지 소장기관마다 이질적인 학술지 정보 관리 시스템을 구축하고 있으며 학술지 정보 기술에도 서로 다른 형식을 사용하고 있기 때문에, 학술지 정보 통합 데이터베이스를 구축및 갱신하고자 할 때는 정보의 형태.의미적 충돌과 시스템 간의 부정합 문제가 야기된다. 본 연구에서는 이러한 문제를 해결하고 학술지 통합 테이터베이스의 자동 구축과 실시간 갱신할 수 있는 있는 효율적인 시스템을 제시한다.

• Journal of the Korean Society for Precision Engineering
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• v.14 no.8
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• pp.65-72
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• 1997

An asymmetrical cross-coupled compensator to improve the contouring performance is proposed. This is a refinement of the structure suggested by Koren. The position loop is closed with a proportional controller as in the uncoupled system. An additional input term proportional to the component of the contour error along the corresponding axis is included. The controller gains are chosen to give an appropriate frequency response and an optimum range for the damping ratio. The effectiveness of the proposed controller is studied by means of digital simulations of the dynamics of the drives and the controller for 4 types of command trajectories: straight line contour, cornering contour, circular contour, elliptic contour. Substantial improvement in contouring performance is obtained for a range of contouring conditions.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.11
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• pp.2066-2072
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• 2010

In this paper, a variable structure dynamic output feedback controller with an transformed sliding surface is designed for the improved robust control of a uncertain system under unmatched system uncertainty, matched input matrix uncertainty, and disturbance satisfying some conditions. This paper is extended from the results of the static output feedback VSS in [9]. To effectively remove the reaching phase problems, an initial condition of the dynamic output is determined. The previous some limitations on the dynamic output feedback variable structure controller is overcome in this systematic design. A stabilizing control is designed to generate the sliding mode on the predetermined sliding surface S=0 and as a results the closed loop exponential stability is obtained and proved together with the existence condition of the sliding mode on S=0 for all unmatched system matrix uncertainties. To show the usefulness of the algorithm, a design example and computer simulations are presented.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.7
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• pp.17-26
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• 2016

This work proposes a 12b 60MS/s 0.18um CMOS Flash-SAR ADC for various systems such as wireless communications and portable video processing systems. The proposed Flash-SAR ADC alleviates the weakness of a conventional SAR ADC that the operation speed proportionally increases with a resolution by deciding upper 4bits first with a high-speed flash ADC before deciding lower 9bits with a low-power SAR ADC. The proposed ADC removes a sampling-time mismatch by using the C-R DAC in the SAR ADC as the combined sampling network instead of a T/H circuit which restricts a high speed operation. An interpolation technique implemented in the flash ADC halves the required number of pre-amplifiers, while a switched-bias power reduction scheme minimizes the power consumption of the flash ADC during the SAR operation. The TSPC based D-flip flop in the SAR logic for high-speed operation reduces the propagation delay by 55% and the required number of transistors by half compared to the conventional static D-flip flop. The prototype ADC in a 0.18um CMOS demonstrates a measured DNL and INL within 1.33LSB and 1.90LSB, with a maximum SNDR and SFDR of 58.27dB and 69.29dB at 60MS/s, respectively. The ADC occupies an active die area of $0.54mm^2$ and consumes 5.4mW at a 1.8V supply.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.3
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• pp.1-11
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• 1999

It is now common practice to utilize the quadrature RF coils to improve the signal-to-noise ratio (SNR) in the Magnetic Resonance Imaging (MRI) System. In addition, to make such an available SNR improvement, it is mandatory to use a well-designed quadrature coupler, which facilitates a perfect 3-dB coupling and quadrature-phase shift. However, the four ports matching condition has to be well considered during the RF excitation and the signal detection period. This work investigates the effects of such a mismatching condition (especially, due to patient) from the analysis, simulation, and real implementation and firstly proposes dynamic loading technique for a quadrature coupler and transmitting/receiving switch module to minimize a patient mismatching and enhance a system reliability. Also, we designed and implemented the quadrature coupler and transmitting/receiving switch module using microstrip. As a result, the SNR of our MRI system using the microstrip quadrature coupler and transmitting/receiving switch module with dynamic load increases 3 dB compared with the old one using USA quadrature switch. Also, the power capability of quadrature coupler and transmitting/receiving switch module is 5-kw peak power. Considering power loss and reduction of size, we used a RT/duroid 6010 substrate with high permittivity and for simulation we use Compact Software.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.7
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• pp.122-130
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• 2013

This work proposes a 12b 100MS/s 45nm CMOS four-step pipeline ADC for high-speed digital communication systems requiring high resolution, low power, and small size. The input SHA employs a gate-bootstrapping circuit to sample wide-band input signals with an accuracy of 12 bits or more. The input SHA and MDACs adopt two-stage op-amps with a gain-boosting technique to achieve the required DC gain and high signal swing range. In addition, cascode and Miller frequency-compensation techniques are selectively used for wide bandwidth and stable signal settling. The cascode current mirror minimizes current mismatch by channel length modulation and supply variation. The finger width of current mirrors and amplifiers is laid out in the same size to reduce device mismatch. The proposed supply- and temperature-insensitive current and voltage references are implemented on chip with optional off-chip reference voltages for various system applications. The prototype ADC in a 45nm CMOS demonstrates the measured DNL and INL within 0.88LSB and 1.46LSB, respectively. The ADC shows a maximum SNDR of 61.0dB and a maximum SFDR of 74.9dB at 100MS/s, respectively. The ADC with an active die area of $0.43mm^2$ consumes 29.8mW at 100MS/s and a 1.1V supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.27-35
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• 2008

This work proposes a 14b 150MS/s 0.13um CMOS ADC for SDR systems requiring simultaneously high resolution, low power, and small size at high speed. The proposed ADC employs a calibration-free four-step pipeline architecture optimizing the scaling factor for the input trans-conductance of amplifiers and the sampling capacitance in each stage to minimize thermal noise effects and power consumption at the target resolution and sampling rate. A signal- insensitive 3-D fully symmetric layout achieves a 14b level resolution by reducing a capacitor mismatch of three MDACs. The proposed supply- and temperature- insensitive current and voltage references with on-chip RC filters minimizing the effect of switching noise are implemented with off-chip C filters. The prototype ADC in a 0.13um 1P8M CMOS technology demonstrates a measured DNL and INL within 0.81LSB and 2.83LSB, at 14b, respectively. The ADC shows a maximum SNDR of 64dB and 61dB and a maximum SFDR of 71dB and 70dB at 120MS/s and 150MS/s, respectively. The ADC with an active die area of $2.0mm^2$ consumes 140mW at 150MS/s and 1.2V.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.3
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• pp.46-55
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• 2016

This work proposes a 13b 100MS/s 45nm CMOS ADC with a high dynamic performance for IF-domain high-speed signal processing systems based on a four-step pipeline architecture to optimize operating specifications. The SHA employs a wideband high-speed sampling network properly to process high-frequency input signals exceeding a sampling frequency. The SHA and MDACs adopt a two-stage amplifier with a gain-boosting technique to obtain the required high DC gain and the wide signal-swing range, while the amplifier and bias circuits use the same unit-size devices repeatedly to minimize device mismatch. Furthermore, a separate analog power supply voltage for on-chip current and voltage references minimizes performance degradation caused by the undesired noise and interference from adjacent functional blocks during high-speed operation. The proposed ADC occupies an active die area of $0.70mm^2$, based on various process-insensitive layout techniques to minimize the physical process imperfection effects. The prototype ADC in a 45nm CMOS demonstrates a measured DNL and INL within 0.77LSB and 1.57LSB, with a maximum SNDR and SFDR of 64.2dB and 78.4dB at 100MS/s, respectively. The ADC is implemented with long-channel devices rather than minimum channel-length devices available in this CMOS technology to process a wide input range of $2.0V_{PP}$ for the required system and to obtain a high dynamic performance at IF-domain input signal bands. The ADC consumes 425.0mW with a single analog voltage of 2.5V and two digital voltages of 2.5V and 1.1V.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.5 s.347
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• pp.54-63
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• 2006

This work proposes a 14b 100MS/s 0.18um CMOS ADC with optimized resolution, conversion speed, die area, and power dissipation to obtain the performance required in the fourth-generation mobile communication systems. The 3-stage pipeline ADC, whose optimized architecture is analyzed and verified with behavioral model simulations, employs a wide-band low-noise SHA to achieve a 14b level ENOB at the Nyquist input frequency, 3-D fully symmetric layout techniques to minimize capacitor mismatch in two MDACs, and a back-end 6b flash ADC based on open-loop offset sampling and interpolation to obtain 6b accuracy and small chip area at 100MS/s. The prototype ADC implemented in a 0.18um CMOS process shows the measured DNL and INL of maximum 1.03LSB and 5.47LSB, respectively. The ADC demonstrates a maximum SNDR and SFDR of 59dB and 72dB, respectively, and a power consumption of 145mW at 100MS/s and 1.8V. The occupied active die area is $3.4mm^2$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.58-68
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• 2006

This work proposes a 10b 250MS/s $1.8mm^2$ 85mW 0.13um CMOS A/D Converter (ADC) for high-performance integrated systems such as next-generation DTV and WLAN simultaneously requiring low voltage, low power, and small area at high speed. The proposed 3-stage pipeline ADC minimizes chip area and power dissipation at the target resolution and sampling rate. The input SHA maintains 10b resolution with either gate-bootstrapped sampling switches or nominal CMOS sampling switches. The SHA and two MDACs based on a conventional 2-stage amplifier employ optimized trans-conductance ratios of two amplifier stages to achieve the required DC gain, bandwidth, and phase margin. The proposed signal insensitive 3-D fully symmetric capacitor layout reduces the device mismatch of two MDACs. The low-noise on-chip current and voltage references can choose optional off-chip voltage references. The prototype ADC is implemented in a 0.13um 1P8M CMOS process. The measured DNL and INL are within 0.24LSB and 0.35LSB while the ADC shows a maximum SNDR of 54dB and 48dB and a maximum SFDR of 67dB and 61dB at 200MS/s and 250MS/s, respectively. The ADC with an active die area of $1.8mm^2$ consumes 85mW at 250MS/s at a 1.2V supply.