• Journal of the Institute of Electronics Engineers of Korea TE
• /
• v.37 no.3
• /
• pp.6-15
• /
• 2000

In this paper, we propose a high speed parallel multiplier with a hierarchical architecture using a fast 4-2 compressor and 6-2 compressor. Generally, the performance of parallel multiplier depends on the processing speed of partial products summation tree with CSA adder. In this paper we propose a new circuit of 4-2 compressor and 6-2 compressor which reduces the propagation delay time, compared with conventional one. We Propose a hierarchical multiplier architecture in order to improve the execution speed of 16$\times$16 parallel multiplier using proposed compressors in this paper and make layout design easily by regular structure. The propagation delay time of the proposed 4-2 compressor circuit was 14% reduced as a result of SPICE simulation, compared with the conventional 4-2 compressor. The total propagation delay time of proposed 16$\times$16 parallel multiplier was 12% reduced using proposed 4-2 compressor and 6-2 compressor.

• School Mathematics
• /
• v.18 no.1
• /
• pp.175-191
• /
• 2016

In the elementary school mathematics textbook that has been revised in 2013, the instructional sequence for teaching addition and subtraction, which had remained unchanged for three decades since 1982, was finally changed in 2013. Particularly, the addition and subtraction of two-digit numbers without regrouping, such as 72+25=97 or 85-24=61, are taught earlier than the composing and decomposing of the number 10 using other numbers. This study examines the appropriacy and validity of these changes. However, the reason for these changes in the national curriculum or teacher's guide could not be determined. Further, several references emphasize the addition of two single-digit numbers, such as 7+8=15, and the subtraction of a single-digit number from a number between 11 and 19, such as 16-9=7, as basic facts. In other countries' textbooks, the teaching of addition and subtraction up to the number 20 is prioritized before teaching the addition and subtraction of two-digit numbers without regrouping. The results of this study indicate that these changes in the instructional sequence in the textbook that was revised in 2013 need to be reconsidered.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.2
• /
• pp.85-92
• /
• 2009

This paper proposes a full-search block-matching motion estimation circuit with hybrid architecture combining systolic arrays and adder trees for an MPEG-4 encoder. The proposed circuit uses systolic arrays for motion estimation with a small number of clock cycles and adder trees to reduce required circuit resources. The interpolation circuit for 1/2 pixel motion estimation consists of six adders, four subtracters and ten registers. We improved the circuit performance by resource sharing and efficient scheduling techniques. We described the motion estimation circuit for integer and 1/2 pixels at RTL in Verilog HDL. The logic-level circuit synthesized by using 130nm standard cell library contains 218,257 gates and can process 94 D1($720{\times}480$) image frames per second.

• Proceedings of the Korea Information Processing Society Conference
• /
• 2000.10a
• /
• pp.849-852
• /
• 2000

본 논문에서는 RSA 암호 시스템의 Montgomery 모듈러 곱셈 알고리듬을 개선한 고속 모듈러 곱셈 알고리듬을 제안하고, Hybrid 구조의 가산기를 사용한 고속 모듈러 곱셈 알고리듬의 설계에 관하여 기술한다. 기존 Montgomery 알고리듬에서는 부분합계산시 2번의 덧셈연산이 요구되지만 제안된 방법에서는 단지 1번의 덧셈 연산으로 부분 합을 계산할 수 있다. 또한 덧셈 연산 속도를 향상시키기 위하여 Hybrid 구조의 가산기를 제안한다. Hybrid 가산기는 기존의 CLA(Carry Look-ahad Adder)와 CSA(Carry Select Adder)알고리듬을 혼합한 구조를 기본으로 하고 있다. 제안된 고속 모듈러 곰셈기는 VHDL(VHSIC Hardware Description Language)을 이용하여 모델링하였고, $Synopsys^{TM}$사의 Design Analyzer를 이용하여 논리합성(Altera 10K lib. 이용)을 수행하였다. 성능 분석을 위하여 Altera MAX+ PLUS II 상에서 타이밍 시뮬레이션을 수행하였고, 실험을 통하여 제안한 방법의 효율성을 입증하였다.

• Education of Primary School Mathematics
• /
• v.21 no.4
• /
• pp.415-430
• /
• 2018

The purpose of this study was to get reflections on teaching numbers and operations for special education from analyzing lessons for counting, addition and subtraction of natural number with counting board for students with autism. In order to attain these purposes, this study analyzed the lessons for counting, addition and subtraction of natural number to students with autism in 4th and 6th graders in special class at regular elementary school using counting board for one hour per week for 30 weeks. According to the analysis, counting board that reveals the structure of numbers becomes an effective mathematical materials, and using the counting strategy and computation strategy can be an effective method of teaching, and it is possible to teach mathematical communication to students with autism. From this result, this study presented suggestions for teaching counting, addition and subtraction for students with disabilities.

• Journal of the Institute of Electronics Engineers of Korea SP
• /
• v.41 no.5
• /
• pp.283-290
• /
• 2004

In this paper, a low-power structure for 512 tap FIR filter in MPEG audio algorithm is proposed. By using CSD(Canonic Signed Digit) form filter coefficients and maximum sharing of input signal sample, it is shown that the number of adders of proposed structure can be minimized. To minimize the number of adders, the proposed structure utilizes the 4 steps of sharing, i.e., common input sharing, linear phase symmetric filter coefficient sharing, block sharing for common input, and common sub-expression sharing. Through Verilog-HDL coding, it is shown that reduction rates in the implementation area and relative power consumption of the proposed structure are 60.3% and 93.9% respectively, comparison to those of the conventional multiplier structure.

• Smart Media Journal
• /
• v.3 no.1
• /
• pp.39-45
• /
• 2014

The partial product matrix of a parallel squarer are symmetric about the diagonal. To reduce the number of partial product bits and the depth of partial product matrix, it can be typically folded, shifted and bit-rearranged. In this paper, an efficient design approach for the combined squarer, capable of operating on either unsigned or signed numbers based on a mode selection signal, is presented. By simulations, it is shown that the proposed combined squarers lead to up to 18% reduction in area, 11% reduction in propagation delay and 9% reduction in power consumption compared with the previous combined squarers.

• Journal of the Korea Institute of Information Security & Cryptology
• /
• v.7 no.1
• /
• pp.15-32
• /
• 1997

본 논문에서는 스트림 암호 시스템에서 사용이 되는 LFSR 을 이용한 이진 수열 발생기중 하나인 Threshold 발생기에 대한 광학적 구현 방법을 새로이 제안하였다. 광학적 구현을 위하여 LCD를 이용하므로서 LFSR 및 Mod 덧셈 연산을 위한 각 비트 값을 표현, 2차원 처리가 가능하게 하였다. Thredshold 발생기의 LFSR기능은 Shdow Casting 기법을 이용하여, 또한 XOR 연산 및 내적 계산을 위한 MOD덧셈 연산은 LCD 가 갖고 있는 편광 특성을 이용하여 광학적으로 구현하였다. 특히 본 논문에서는 Mod 2 덧셈 연산을 위한 새로운 광학적 구현 방법인 RSPM 을 제안하므로서 연산 결과 값 측정과 LCD 상의 데이타 값 표현 과정을 제외한 전 부분을 완전한 광학적 방법으로 처리가 가능하게 하였다. 본 논문에서 제안한 광 Threshold 암호 시스템은 기존의 전자적인 H/W 구현 방법에서 문제가 되어오던 Tapping Point의 개수에 대한 한계성을 극복할 수 있는 장점을 지니고 있으며, 또한 2차원 데이타인 영상용 암호화 시스템의 광학적 구현에 그 응용이 가능하다.

• Proceedings of the Korea Information Processing Society Conference
• /
• 2021.11a
• /
• pp.313-314
• /
• 2021

최근 개인 정보 보호를 위해 주목 받고 있는 동형암호 알고리즘은 암호화된 상태로 덧셈과 곱셈 연산이 가능하여, 연산을 위한 복호화 과정 없이 데이터에 대한 가공이 가능하다. 따라서 이러한 동형암호 알고리즘이 개인 정보 보호를 위한 방법으로 떠오르고 있으며, 특히 완전동형암호 알고리즘의 경우 덧셈과 곱셈 연산을 모두 지원하며, 유효 연산 횟수에도 제한이 없어 응용 분야에서 널리 활용될 것으로 예상된다. 그러나, 완전동형암호 알고리즘의 경우 암호문의 크기가 평문대비 크게 증가하고, 다항식으로 구성된 암호문의 덧셈 및 곱셈 연산도 복잡하여 이에 대한 가속이 필요한 실정이다. 이에 FPGA 기반의 동형암호 가속기 개발이 많이 연구되고 있으며, 이를 통해 동형암호 연산의 특징을 이해하고 가속기 연구 동향을 알아보려 한다.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.1
• /
• pp.1-6
• /
• 2008

There are many possible representations in denoting both positive and negative numbers in the binary number system to be applicable to the complexity of the hardware implementation, arithmetic speed, appropriate application, etc. Among many possibilities, the signed-magnitude representation, which keeps one sign bit and magnitude bits separately, is intuitively appealing for humans, conceptually simple, and easy to negate by flipping the sign bit. However, in the signed-magnitude representation, the actual arithmetic operation to be performed may require magnitude comparison and depend on not only the operation but also the signs of the operands, which is a major disadvantage. In a simple conceptual approach, addition/subtraction of two signed-magnitude numbers, requires comparator circuits, selective pre-complement circuits, and the adder circuits. In this paper circuits to obtain the difference of two numbers are designed without adopting explicit comparator circuits. Then by using the difference circuits, a universal signed-magnitude adder/subtracter is designed for the most general operation on two signed numbers.