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Low-power MPEG audio filter implementation using Arithmetic Unit  

장영범 (상명대학교 공과대학 정보통신공학과)
이원상 (상명대학교 대학원 컴퓨터정보통신공학과)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SP / v.41, no.5, 2004 , pp. 283-290 More about this Journal
Abstract
In this paper, a low-power structure for 512 tap FIR filter in MPEG audio algorithm is proposed. By using CSD(Canonic Signed Digit) form filter coefficients and maximum sharing of input signal sample, it is shown that the number of adders of proposed structure can be minimized. To minimize the number of adders, the proposed structure utilizes the 4 steps of sharing, i.e., common input sharing, linear phase symmetric filter coefficient sharing, block sharing for common input, and common sub-expression sharing. Through Verilog-HDL coding, it is shown that reduction rates in the implementation area and relative power consumption of the proposed structure are 60.3% and 93.9% respectively, comparison to those of the conventional multiplier structure.
Keywords
arithmetic unit; common sub-expression; MPEG audio; CSD form;
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