1 |
J. Pihl and E. Aas, "A multiplier and squarer generator for high performance DSP applications," Proc. IEEE 39th Midwest Symp. on Circuits and Systems, pp. 109-112, 1996
|
2 |
R. K. Kolagotla , W. R. Griescbach, and H. R. Srinivas, "VLSI implementation of a 350 MHz 0.35 8 bit merged squarer, Electronic Letters, vol. 34, pp. 47-48, Jan. 1998 .
DOI
ScienceOn
|
3 |
K. E. Wires, M. J. Schulte, L. P. Marquette, and P. I. Balzola, "Combined unsigned and two's complement squarers," Proc. 33rd Asilomar Conference on Signals, Systems, and Computers, pp. 1215-1219, 1999.
|
4 |
K. J. Cho and J. G. Chung, "Parallel squarer design using pre-calculated sums of partial products," Electronics Letters, vol. 43, pp. 1414-1416, Dec. 2007.
DOI
|
5 |
E. G. Walters, M. J. Schulte, and M. G. Arnold, "Truncated squarers with constant and variable correction," Proc. SPIE: Advanced Signal Processing Algorithms, Architectures, and Implementations XIII, Denver, Co, Aug. 2004.
|
6 |
A. G. M. Strollo and D. D. Caro, "Booth folding encoding for high performance squarer circuits," IEEE Trans. Cirucits and Systems II, vol. 50, pp. 250-254, May 2003.
|
7 |
C. S. Wallace, "Suggestion for a fast multiplier," IEEE Trans. Electronic Computers, vol. EC-13, pp. 14-17, 1964.
DOI
ScienceOn
|
8 |
L. Dadda, "Some Schemes for parallel multipliers," Alta Frequenza, vol. 34, pp. 349-356, 1965.
|
9 |
K. C. Bickerstaff, M. J. Schulte, and E. E. Swartzlander, Jr., "Parallel reduced area multipliers," Journal of VLSI Signal Processing, vol. 9. pp. 181-191, 1995.
DOI
|
10 |
V. G. Oklodgzija and D. Villeger, and S. S. Liu, "A method for speed optimized partial product reduction and generation for fast parallel multipliers using and algorithmic approach," IEEE Trans. Computers, vol. 45. no. 3, pp. 294-305, 1996.
|