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A Design of Comparatorless Signed-Magnitude Adder/Subtracter  

Chung, Tae-Sang (Dept. of Electrical and Electronics Engineering, University of Chung-Ang)
Kwon, Keum-Cheol (Dept. of Electrical and Electronics Engineering, University of Chung-Ang)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.45, no.1, 2008 , pp. 1-6 More about this Journal
Abstract
There are many possible representations in denoting both positive and negative numbers in the binary number system to be applicable to the complexity of the hardware implementation, arithmetic speed, appropriate application, etc. Among many possibilities, the signed-magnitude representation, which keeps one sign bit and magnitude bits separately, is intuitively appealing for humans, conceptually simple, and easy to negate by flipping the sign bit. However, in the signed-magnitude representation, the actual arithmetic operation to be performed may require magnitude comparison and depend on not only the operation but also the signs of the operands, which is a major disadvantage. In a simple conceptual approach, addition/subtraction of two signed-magnitude numbers, requires comparator circuits, selective pre-complement circuits, and the adder circuits. In this paper circuits to obtain the difference of two numbers are designed without adopting explicit comparator circuits. Then by using the difference circuits, a universal signed-magnitude adder/subtracter is designed for the most general operation on two signed numbers.
Keywords
Signed-Magnitude Number Representation; Difference Circuits; Adder/Subtracter; Complement;
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