• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.2
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• pp.14-25
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• 1999

The IEEE standard 1149.1, which was proposed to increase the observability and the controllability in I/O pins, makes it possible the board level testing. In the boundary-scan environments, many shift operations are required due to their serial nature. This increases the test application time and the test application costs. To reduce the test application time, the method based on the parallel opereational multiple scan paths was proposed, but this requires the additional I/O pins and the internal wires. Moreover, it is difficult to make the designs in conformity to the IEEE standard 1149.1 since the standard does not support the parallel operation of data shifts on the scan paths. In this paper, the multiple scan path access algorithm which controls two scan paths simultaneously with one test bus is proposed. Based on the new algorithm, the new algorithm, the new board level BIST architecture which has a relatively small area overhead is developed. The new BIST architecture can reduce the test application time since it can shift the test patterns and the test responses of two scan paths at a time. In addition, it can reduce the costs for the test pattern generation and the test response analysis.

• Journal of Digital Contents Society
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• v.13 no.4
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• pp.491-500
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• 2012

In this paper, a new loopback BIST structure which is effective to test RF transceiver chip and LNA(Low Noise Amplifier) in the chip is presented. Because the presented BIST structure uses a baseband processor in the chip as a tester while the system is under testing mode, the developed test technique has an advantage of performing test application and test evaluation in effectiveness. The presented BIST structure can change high frequency test output signals to a low frequency signals which can make the CUT(circuits under test) tested easily. By using this technique, the necessity of RF test equipment can be mostly reduced. The test time and test cost of RF circuits can be cut down by using proposed BIST structure, and finally the total chip manufacturing costs can be reduced.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.935-938
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• 1999

메모리 테스트는 Built-In Self Test(BIST)와 같이 메모리에 내장된 회로를 통하여 자체 점검하는 방법과 테스터를 통하여 생성된 패턴을 주입하는 방법이 있다. 테스트 패턴 생성방법으로는 각각의 고장모델에 대한 테스트 패턴을 deterministic하게 생성해주는 방법과 Pseudo Random Pattern Generator(PRPG)를 이용하여 생성하는 경우로 구분할 수 있다. 본 연구에서는 PRPG를 패턴 생성기로 사용하여 여러 가지 메모리의 결함을 대표한다고 볼 수 있는 Static 및 Dynamic Neighborhood Pattern Sensitive Fault(NPSF) 등 다양한 종류의 고장을 점검할 수 있도록 메모리 BIST를 구성하였다. 기존의 Linear Feedback Shift Register(LFSR)보다 본 연구에서 제안하는 Linear Hybrid Cellular Automata(LHCA)를 이용한 PRPG가 높고 안정된 고장 점검도를 나타내었다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.12
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• pp.24-30
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• 2010

In recent memories, repair is an unavoidable method to maintain its yield and quality. The probability of defect occurence on spare lines has been increased through the growth of the density of recent memories with 2 dimensional spare architecture. In this paper, a new analysis region virtualization scheme is proposed. the analysis region virtualization scheme can be applied with any BIRA (built-in redundancy analysis) algorithms without the loss of their repair rates. The analysis region virtualization scheme can be a viable solution for BIRA considering the faulty spare lines of the future high density memories.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.8
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• pp.29-35
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• 2010

In this paper we propose a new pattern generator for a BIST architecture that can reduce the power consumption during test application. The principle of the proposed method is to reconstruct an LFSR circuit to reduce WSAs of the heavy nodes by suppressing the heavy inputs. We propose algorithms for finding heavy nodes and heavy inputs. Using the Modified LFSR which consists of some AND/OR gates trees and an original LFSR, BIST applies modified test patterns to the circuit under test. The proposed BIST architecture with small hardware overhead effectively reduces the average power consumption during test application while achieving high fault coverage. Experimental results on the ISCAS benchmark circuits show that average power reduction can be achieved up to 30.5%.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.69-81
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• 2008

The density of Memory has been increased by great challenge for memory technology, so elements of memory become smaller than before and the sensitivity to faults increases. As a result of these changes, memory testing becomes more complex. The number of storage elements is increased per chip, and the cost of test becomes more remarkable as the cost per transistor drops. Proposed design doesn't need to control from outside environment, because it integrates into memory. The proposed scheme supports the various memory testing algorithms. Consequently, the proposed one is more efficient in terms of test cost and test data to be applied. Moreover, we proposed a reallocation algorithm for faulty memory parts. It has an efficient reallocation scheme with row and column redundant memory. Previous reallocation information is obtained from faulty memory every each tests. However proposed scheme avoids to this problem. because onetime test result from reallocation information can save to flash memory. In this paper, a reallocation scheme has been increased efficiency because of using flash memory.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.11
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• pp.30-36
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• 2010

In recent memories, repair is an unavoidable method to maintain its yield and quality. Although many word oriented memories as well as embedded memories in system-on-chip (SOC) consists of multiple local memory blocks with a global spare architecture, most of previous studies on built-in redundancy analysis (BIRA) algorithms have focused on single memory block with a local spare architecture. In this paper, a new BIRA algorithm for multiple blocks with a global spare architecture is proposed. The proposed BIRA is basd on CRESTA which is able to achieve optimal repair rate with almost zero analysis time. In the proposed BIRA, all repair solutions for local memory blocks are analyzed by local analyzers which belong to each local memory block and then compared sequentially and judged whether each solution can meet the limitation of the global spare architecture or not. Experimental results show that the proposed BIRA achieves much faster analysis speed compared to previous BIRAs with an optimal repair rate.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.8 s.350
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• pp.27-34
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• 2006

During Built-In Self-Test(BIST), The set of patterns generated by a pseudo-random pattern generator may not provide sufficiently high fault coverage and many patterns were undetected fault. In order to reduce the test time, we can remove useless patterns or change from them to useful patterns. In this paper, we reseed modify the pseudo-random and use an additional bit flag to improve test length and achieve high fault coverage. the fat that a random tset set contains useless patterns, so we present a technique, including both reseeding and bit modifying to remove useless patterns or change from them to useful patterns, and when the patterns change, we choose number of different less bit, leading to very short test length. the technique we present is applicable for single-stuck-at faults. the seeds we use are deterministic so 100% faults coverage can be achieve.

• Proceedings of the KIEE Conference
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• 2009.07a
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• pp.1931_1933
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• 2009

NoC 기반 시스템이 적용되는 설계는 시스템 크기가 커짐에 따라 칩 테스트 문제도 동시에 제기 되고 있다. 이에 따라 NoC 기반의 시스템의 테스트 시간을 줄일 수 있는 internal test 방식의 새로운 BIST(Built-in Self-Test) 구조에 관한 연구를 하였다. 기존의 NoC 기반 시스템의 BIST 테스트 구조는 각각의 router와 core에 BIST logic과 random pattern generator로 LFSR(Linear Feedback Shift Register)을 사용하여 연결하는 individual 방식과 하나의 BIST logic과 LFSR을 사용하여 각각의 router와 core에 병렬로 연결하는 distributed 방식을 사용한다. 이때, LFSR에서 생성된 테스트 벡터가 router에 사용되는 FIFO 메모리를 통과하면서 생기는 테스트 타임 증가를 줄이기 위하여 shift register 형태의 FIFO 메모리를 변경하였다 제안된 방법에서 테스트 커버리지 98%이상을 달성하였고, area overhead면에서 효과를 볼 수 있다.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.8
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• pp.1-9
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• 1998

A new parallel test algorithm and a built-in self test (BIST) architecture are developed to test various types of functional faults efficiently in content addressable memories (CAMs). In test mode, the read oepratin is replaced by one parallel content addressable search operation and the writing operating is performed parallely with small peripheral circuit modificatins. The results whow that an efficient and practical testing with very low complexity and area overhead can be achieved.