1 |
Al-Yamani A., and E.J. McCluskey, 'Built-In Reseeding for Serial BIST,' VLSI Test Symposium, Apr., 03
|
2 |
Eichelberger, E.B., and E. Lindbloom, F. Motica, and J. Waicukauski, 'Weighted Random Pattern Testing Apparatus and Method,' US Patent 4,801,870, Jan. 89
|
3 |
Hellebrand, S., B. Reeb, S. Tarnick, and H.-J. Wunderlich, 'Pattern Generation for a Deterministic BIST Scheme,' 'Proc. of International Conference on Computer-Aided Design(ICCSAD), pp.88-94, 1995
DOI
|
4 |
Touba, N. A. and E.J. McCluskey, 'Altering Bit Sequence to Contain Predetermined Patterns,' US Patent 6,061,818, May, 2000
|
5 |
Touba, N.A., and E.J. McCluskey, 'Test Point Insertion Based on Path Tracing,' Proc. of VLSI Test Symposium, pp. 2-8, 1996
DOI
|
6 |
Touba, N.A., and E.J. McCluskey, 'Test Point Insertion Based on Path Tracing,' Proc. of VLSI Test Symposium, pp. 2-8, 1996
DOI
|
7 |
Chiang, C.-H., and S.K. Gupta, 'Random Pattern Testable Logic Synthesis,' Proc. of International Conference on Computer-Aided Design (ICCAD) , pp. 125-128, 1994
|
8 |
Eichelberger, E. B., and E. Lindbloom, 'Random Pattern Coverage Enhancement and Diagnosis for LSSD Logic Self-Test,' IBM Journal of Research and Development, Vol. 27, No.3, pp. 265-272, May. 1983
DOI
ScienceOn
|