• Proceedings of the KIPE Conference
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• 2013.07a
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• pp.165-166
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• 2013

기존의 위상천이 풀 브리지 DC/DC 컨버터의 경우 변압기의 누설 인덕턴스와 정류 스위치의 기생 출력 캐패시턴스 사이의 공진으로 인하여 정류 스위치에 스파이크 전압이 발생하며, 이는 시스템의 전력 변환 효율을 감소시킨다. 최근에 보조 DC/DC 컨버터를 사용하여 클램핑 캐패시터에서 흡수된 에너지를 부하로 회기시키는 방법이 연구되고 있으나, 보조 DC/DC 컨버터를 설계하기 위한 정확한 분석은 제시되지 않았다. 따라서, 본 논문에서는 2차 측 정류기의 공진 전압을 저감할 수 있는 비동기식 능동형 스너버 회로의 설계방법을 제안한다. 또한, 초기 기동 시에 발생되는 큰 공진에너지를 히스테리시스 회로를 이용하여 저항을 통해 소모시킴으로써 보조 DC/DC 컨버터의 자성소자를 최소화할 수 있다. 본 논문에서는 제안된 방식의 타당성을 검증하기 위하여 이론적으로 분석하며, 450W급 시작품을 제작하여 제안방식의 타당성을 검증하였다.

• The Journal of the Korea institute of electronic communication sciences
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• v.8 no.11
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• pp.1633-1640
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• 2013

In this paper, noise parameters for high frequency modeling of dual-gate FET are extracted and analyzed. To extract thermal noise parameter of dual gate, noise characteristics are measured by changing input impedance of noise source using Tuner, and the influence of pad parasitic elements are subtracted using open and short dummy structure. Measured results indicated that the dual-gate FET is improved the noise figure by 0.2dB compared with conventional cascode structure FET at 5GHz, and it confirmed that the noise figure has dropped due to reduction of capacitances between the drain and source, gate and drain by simulation and analysis of small-signal parameters.

• Journal of IKEEE
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• v.23 no.3
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• pp.878-882
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• 2019

XOR(exclusive-OR)-XNOR(exclusive NOR) circuit is a basic component of 4-2 compressor for high performance arithmetic operation. In this paper we propose an energy efficient XOR-XNOR circuit. The proposed circuit is reduced the internal parasitic capacitance in critical path and implemented with 8 transistors. The circuit produces a perfect output signals for all input combinations. Compared with the previous circuits, the proposed circuit has a 14.5% reduction in propagation delay time and a 1.7% increase in power consumption. Therefore, the proposed XOR-XNOR is reduced power-delay- product (PDP) by 13.1% and energy-delay-product (EDP) by 26.0%. The proposed circuits are implemented with standard CMOS 0.18um technology and verified through SPICE simulation with 1.8V supply voltage.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.8 s.338
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• pp.53-60
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• 2005

Recently, sub-micron CMOS technologies have taken the place of III-V materials in a number of areas in integrated circuit designs, in particular even for the applications of gjgabit optical communication applications due to its low cost, high integration level, low power dissipation, and short turn-around time characteristics. In this paper, a four-channel transimpedance amplifier (TIA) array is realized in a standard 0.35mm CMOS technology Each channel includes an optical PIN photodiode and a TIA incorporating the fully differential regulated cascode (RGC) input configuration to achieve effectively enhanced transconductance(gm) and also exploiting the inductive peaking technique to extend the bandwidth. Post-layout simulations show that each TIA demonstrates the mid-band transimpedance gain of 59.3dBW, the -3dB bandwidth of 2.45GHz for 0.5pF photodiode capacitance, and the average noise current spectral density of 18.4pA/sqrt(Hz). The TIA array dissipates 92mw p in total from a single 3.3V supply The four-channel RGC TIA array is suitable for low-power, high-speed optical interconnect applications.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.1
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• pp.20-26
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• 2016

This paper presents an X-band two-stage power amplifier using GaN-HEMT. Two-stage structure was adopted to take its high gain and simple inter-stage matching network. Based on a 3D EM simulation, the bond-wire inductance and the parasitic capacitance were predicted. By reducing bond-wire inductance, Q of the matching network is decreased and the bandwidth is improved. The implemented two-stage PA shows a power gain of more than 16 dB, saturated output power of more than 42.5 dBm, and a efficiency of more than 35 % in frequency range of 8.1~8.5 GHz with an operating voltage of 40 V.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.4A
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• pp.439-446
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• 2004

This paper describes high speed and low power design techniques for an 8-bit 500MSamples/s CMOS 2-step ADC. Instead of the conventional closed-loop architecture, the newly proposed ADC adopts open-loop architecture and uses a reset-switch to reduce loading time in an environment of big parasitic-capacitances of mux-array. An analog-latch is also used to reduce power consumption. Simulation result shows that the ADC has the SNDR of 46.91㏈ with a input frequency of 103MHz at 500Msample/s and consumes 203㎽ with a 1.8V single power supply. The chip is designed with a 0.18mm 1-poly 6-metal CMOS technology and occupies active area of 760${\mu}{\textrm}{m}$*800${\mu}{\textrm}{m}$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.10
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• pp.687-698
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• 2001

This paper presents a three dimensional stacked pad area away (PAA) package configuration as an implementation method of radio frequency (RF) circuits. 224MHz RF circuits of intelligence traffic system(ITS) were constructed with the stacked PAA RF pakage configuration. In the process of manufacturing the stacked PAA RF pakage, RF circuits were partitioned to subareas following their function and operating frequency. Each area of circuits separated to each subunits. The operating characteristics of RF PAA package module and the electrical properties of each subunits were examined. The measurement of electrical parameters for solder balls which were interconnects for stacked PAA RF packages showed that the parasitic capacitance and inductance were 30fF and 120pH, respectively, which might be negligible in PAA RF packaging system. HP 4396B network/spectrum analyzer revealed that the amplification gain of a receiver and transmitter at 224 MHz was 22dB and 27dB, respectively. The gain was 3dB lower than designed values. The difference was probably generated from fabrication process of the circuits by employing commercial standard

• Journal of Satellite, Information and Communications
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• v.10 no.2
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• pp.80-85
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• 2015

In this paper, we present, an indstrial RFID layered microstrip patch antenna is designed using an inset feed method in order to improve recognition rates in a long distance as tags are attached to metal object by improving a problem of feeding power in fabricating metal tags and reducing effects of metallic object. The inset feed shows a distinctive characteristic that has no separation between emitters and feed lines differing from a structure with the conventional inductive coupling feed. This structure makes possible to produce a type that presents a low antenna height and enables impedance coupling for tag chips. Although it shows a difficulty in the impedance coupling due to increases in the parasite capacitance between a ground plane and an emitter in an antenna according to decreases in the height of a tag antenna, it may become a merit in designing the tag antenna because the antenna impedance can be determined as an inductive manner if a shorted structure is used for feeding power. Therefore, in this paper the microstrip patch antenna is designed as a modified type and applies the inset feed in order to reduce effects of metallic objects where the antenna is be attached. Also, the antenna uses a multi-layer structure that includes a metal plate between radiator and ground instead of using a single layer.

• Journal of the Microelectronics and Packaging Society
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• v.16 no.4
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• pp.9-15
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• 2009

Compared to the flip-chip process using solder bumps, Cu pillar bump technology can accomplish much finer pitch without compromising stand-off height. Flip-chip process with Cu pillar bumps can also be utilized in radio-frequency packages where large gap between a chip and a substrate as well as fine pitch interconnection is required. In this study, Cu pillars with and without Sn caps were electrodeposited and flip-chip-bonded together to form the Cu-Sn-Cu sandwiched joints. Contact resistances and die shear forces of the Cu-Sn-Cu sandwiched joints were evaluated with variation of the height of the Sn cap electrodeposited on the Cu pillar bump. The Cu-Sn-Cu sandwiched joints, formed with Cu pillar bumps of $25-{\mu}m$ diameter and $20-{\mu}m$ height, exhibited the gap distance of $44{\mu}m$ between the chip and the substrate and the average contact resistance of $14\;m{\Omega}$/bump without depending on the Sn cap height between 10 to $25\;{\mu}m$.

• Journal of the Microelectronics and Packaging Society
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• v.16 no.3
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• pp.67-73
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• 2009

Compared to the chip-bonding process utilizing solder bumps, flip chip process using Cu pillar bumps can accomplish fine-pitch interconnection without compromising stand-off height. Cu pillar bump technology is one of the most promising chip-mounting process for RF packages where large gap between a chip and a substrate is required in order to suppress the parasitic capacitance. In this study, Cu pillar bumps and Sn bumps were electroplated on a chip and a substrate, respectively, and were flip-chip bonded together. Contact resistance and chip shear force of the Cu pillar bump joints were measured with variation of the electroplated Sn-bump height. With increasing the Sn-bump height from 5 ${\mu}m$ to 30 ${\mu}m$, the contact resistance was improved from 31.7 $m{\Omega}$ to 13.8 $m{\Omega}$ and the chip shear force increased from 3.8 N to 6.8 N. On the contrary, the aspect ratio of the Cu pillar bump joint decreased from 1.3 to 0.9. Based on the variation behaviors of the contact resistance, the chip shear force, and the aspect ratio, the optimum height of the electroplated Sn bump could be thought as 20 ${\mu}m$.