• Proceedings of the Korean Society of Precision Engineering Conference
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• 2005.10a
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• pp.212-215
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• 2005

The needs of larger screen in mobile device would be increased as the time of ubiquitous and convergence is coming. And, the type of mobile device has been evolved from bar, slide to row. Recently, the study on the multi-display screen which has seamless gap between two display panel has been published, and moreover the System On Chip(SOC) design strategy of core chip has been the most promising Field-Programmable Gate Array(FPGA) technology in the display system. Therefore, in this paper, we proposed the design technique of SOC and evaluated the effectiveness with Very high speed Hardware Description Language(VHDL) Intellectual Property (IP) for the operation of multi display device driver. Also, This IP design would be to allow any kind of user interface in control system.

• Proceedings of the Korea Information Processing Society Conference
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• 2007.11a
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• pp.1040-1041
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• 2007

본 논문은 차세대 위성 개발을 위한 선행 연구의 일환으로, 다양한 플랫폼에 적용할 수 있는 위성 전자 전산 시스템 개발 검증 장비의 구성 요소인 상/하향 명령 처리 장치를 PC 에서 구동할 수 있도록 개발한 것이다. 이 PC 기반의 상/하향명령처리 시험환경은 위성의 Flight Software 로직의 검증용으로도 활용될 수 있다.

• Aerospace Engineering and Technology
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• v.4 no.1
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• pp.57-65
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• 2005

Due to the future of a large size satellite like Geo-stationary orbit satellite, KARI has progressed the construction of Large Thermal Vacuum Chamber(LTVC) with Φ8mXL10m, which simulates the orbit environment at space. The space environment can be characterized as very harsh conditions. Once the spacecraft is launched and enters its orbit, the satellite is exposed to this space environment. The continuous exposure to such space environment could cause malfunction of major parts of the spacecraft, which could lead to the failure of the entire mission. Due to the fact that space environment is completely different from that of the ground, the satellite that functioned normally on the ground could show some unexpected malfunction in space environment. For this reason, the performance of the spacecraft must be confirmed under the simulated conditions of the space environment. This document includes LTVC control logic, Interlock by which the LTVC can be controlled more safely and efficiently.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.15 no.4
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• pp.1850-1858
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• 2014

The object of this study is to develop an cooling control algorithm for electronics devices of the electric vehicle. In order to estimate the existing cooling control logic of the electronic devices for the small and medium sized electric vehicle, the experiments on the coolant temperature variation of the cooling system were conducted under 4 different seasons conditions. As a result, the existing cooling control logic were overcooled when it was compared with the reference temperature for a required cooling load. In addition, the newly developed optimum cooling control logic for improving the mileages of the tested electric vehicle with consideration of the ambient temperature, vehicle speed, and refrigerant temperature of the air conditioning on/off is necessary.

• Journal of Internet of Things and Convergence
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• v.6 no.1
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• pp.97-102
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• 2020

Multi-Channel Switch ICs for IoT have integrated several solid state structure low ON-resistance bi-directional relay MOS switches with level shifter to drive high voltage and they should be independently controlled by external serialized logic control. These devices are designed for using in applications requiring high-voltage switching control by low-voltage control signals, such as medical ultra-sound imaging, ink-jet printer control, bare board open/short and leakage test system using Kelvin 4-terminal measurement method. This paper describes implementation of analog switch control block and its verification using Field programmable Gate Array (FPGA) test pattern generation. Each block has been implemented using Verilog hardware description language then simulated by Modelsim and prototyped in a FPGA board. Compare to conventional IC, The proposed architecture can be applied to fields where multiple entities need to be controlled simultaneously in the IoT environment and the proposed pattern generation method can be applied to test similar types of ICs.

• Journal of the Korean Society of Propulsion Engineers
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• v.19 no.1
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• pp.87-97
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• 2015

In general, such ground based methods are utilized to validate maneuvering and attitude control logics of a spacecraft by a simulation with a flight software at a design phase and a integrated function test with actual hardwares at a system level. Recently, varification researches using operating simulators are getting increase using compact and precise components under a ground condition. The present paper investigates and summarized the development trend of cold gas propulsion systems for the spacecraft simulators and their major performance characteristics to derive fundamental data which are necessary for a conceptual design of the simulator.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.12
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• pp.80-86
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• 2009

In this paper, we present a new charge pump circuit feasible for the implementation with standard twin-well CMOS process technology. The proposed charge pump employs PMOS-switching dual charge-transfer paths and a simple two-phase clock. Since charge transfer switches are fully turned on during each half of clock cycle, they transfer charges completely from the present stage to the next stage without suffering threshold voltage drop. During one clock cycle, the pump transfers charges twice through two pumping paths which are operating alternately. The performance comparison by simulations and measurements demonstrates that the proposed charge pump exhibits the higher output voltage, the larger output current and a better power efficiency over the traditional twin-well charge pumps.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.31 no.10
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• pp.89-96
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• 2003

In this paper, a CCSDS(Consultative Committee for Space Data Systems) telecommand(TC) decryptor for the security of geostationary communications satellite was implemented. For the confidentiality of CCSDS TC datalink security, Option-A which implements the security services below the transfer sublayer was selected. Also CFB(Cipher Feedback) operation mode of DES(Data Encryption Standard) was used for the encryption of 56-bit data bits in 64-bit codeblock. To verify Decryptor function, the DES CFB logic implemented on A54SX32 FPGA(Field Programmable Gate Array) was integrated with interface and control logics in a PCB(Printed Circuit Board). Using a function test PC, the encrypted codeblocks were generated, transferred into the decryptor, decrypted, and the decrypted codeblocks were transmitted to the function test PC, and then compared with the source codeblocks. Through LED(Light Emitting Diode) ON operation by driving the relay related to Op-code decoded and the comparison between the codeblock output waveforms measured and those simulated, the telecommand decryptor function was verified.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.6B
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• pp.456-468
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• 2008

In this paper, we design Input/Output modules as a preference work for implementation of hybrid two stage AWG based WDM-PON and verify operations of each function modules through the logic simulation. This WDM-PON system provides service to 128 ONUs through 32 wavelength and one wavelength is shared for upstream transmission with four ONU while each wavelength is allocated to each ONU for downstream transmission. The designed WDM-PON MAC chip is based on sub-MAC which consists of one control unit and reception unit and four transmission unit. To design the reception and transmission unit of sub-MAC, we define the functions of the sub-MAC, pins of the modules, control signal and timing of each signal. We intend to design MAC chip with 1Gbps transmission rate. Thus the designed MAC chip is worked on 125MHz clock rate. We define FSM and design Input/Output modules with VHDL. The logic simulation of the modules is executed by the ModelSIM simulator.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.4
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• pp.913-920
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• 2011

In this paper, a logic process based 1-kbit EEPROM IP for RFID tag chips of 900MHz is designed. The cell array of the designed 1-kbit EEPROM IP is arranged in a form of four blocks of 16 rows x 16 columns, that is in a two-dimensional arrangement of one-word EEPROM phantom cells. We can reduce the IP size by making four memory blocks share CG (control gate) and TG (tunnel gate) driver circuits. We propose a TG switch circuit to supply respective TG bias voltages according to operational modes and to keep voltages between devices within 5.5V in terms of reliability in order to share the TG driver circuit. Also, we can reduce the power consumption in the read mode by using a partial activation method to activate just one of four memory blocks. Furthermore, we can reduce the access time by making BL (bit line) switching times faster in the read mode from reduced number of cells connected to each column. We design and compare two 1-kbit EEPROM IPs, two blocks of 32 rows ${\times}$ 16 columns and four blocks of 16 rows ${\times}$ 16 columns, which use Tower's $0.18{\mu}m$ CMOS process. The four-block IP is smaller by 11.9% in the layout size and by 51% in the power consumption in the read mode than the two-block counterpart.