• Journal of Energy Engineering
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• v.23 no.4
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• pp.130-140
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• 2014

Rotary kiln burner has been developed continuously to improve process efficiency and exhaust emission. In this study, the characteristics of the flame and exhaust emission were numerically analyzed according to the diameter of primary air nozzle, equivalent ratio of burner, and equivalent ratio at center and side nozzle for development of multi-nozzle burner in the COG(Coke Oven Gas) rotary kiln for sintering iron ore. The results indicated that the flame length and $NO_x$ emission increase, as the diameter of primary air nozzle and equivalent ratio of burner increase. And according to the change of equivalent ratio at the center and the side of the nozzle, the flame length and average temperature in the kiln show very little change but the $NO_x$ emission shows obvious difference. In conclusion, the best design conditions which have satisfying flame length, average temperature and $NO_x$ emission are as follows: $D_2/D_1$ is 1.33, equivalent ratio of burner is 1.25 and center nozzle conditions are Rich.

• Proceedings of the KWS Conference
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• 2010.05a
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• pp.79-79
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• 2010

저온용 무연 솔더의 대표 조성으로 고려되고 있는 Sn-58Bi(융점: $138^{\circ}C$) 공정(eutectic) 조성은 우수한 강도에도 불구하고 연성(ductility) 측면에서의 문제점이 지속적으로 보고되고 있다. 따라서 이 합금계의 연성을 최대로 개선시킬 수 있으면서도 실제 상용화가 가능한 합금 조성의 개발 연구가 요청된다. 본 연구에서는 Sn-Bi 2원계 조성에서 최대의 연성을 나타내는 것으로 보고된 Sn-40Bi 조성에 미량의 합금원소를 첨가함으로써 최대의 연성을 확보하는 한편, 그 연성 특성이 변형속도에 어느 정도 민감한지를 인장 실험을 통해 결정하고자 하였다. 합금원소로는 0.1~0.5 wt%의 Ag, Mn, In, Cu를 선택하였으며, 인장 시편을 제조하여 $10^{-2}$, $10^{-3}$, $10^{-4}\;s^{-1}$의 3종류로 변형속도를 변형시켜가며 응력-변형 곡선(stress-strain curve)을 측정하였고, 조성별, 변형속도별로 최대인장강도(ultimate tensile stress, UTS) 및 연신율 결과들을 정리하였다. 합금원소를 첨가한 조성의 경우는 모든 시험 조건에서 Sn-40Bi보다 우수한 연신률을 나타내는 것으로 측정되었으나, $10^{-2}\;s^{-1}$의 빠른 변형속도에서는 그 향상 정도가 상대적으로 감소하는 경향이 관찰되었다. 특히 Sn-40Bi-0.5Ag 조성의 경우 느린 변형속도에서 특히 눈에 띄는 연신률 값을 나타내며, 모든 변형속도 조건에서 가장 우수한 연성을 나타내었다. 한편 Sn-40Bi-0.1Cu 조성의 경우 변형속도에 따른 연신률의 변화 정도, 즉, 변형속도에 따른 연신률의 민감도가 매우 커 $10^{-4}\;s^{-1}$ 속도에서는 Sn-40Bi-0.5Ag에 버금가는 연신률 값이 측정되었으나, $10^{-2}\;s^{-1}$ 속도에서는 가장 나쁜 연신률 특성을 보여주었다. Sn-40Bi-0.2Mn 조성은 최고의 연신률 향상 특성을 나타내지는 않았으나, In을 첨가한 경우보다는 대체적으로 우수한 연성을 나타내었다. 이상의 각 합금별 연성 특성은 인장시험 전의 미세조직 관찰 결과와 인장시험 후 파면부의 조직변화 관찰 결과로부터 해석되었다. 그 결과 석출상의 형성 여부, 인장 시험 중 재결정 조직의 형성 여부, 라멜라(lamellar) 조직의 분율과 라멜라 간격(lamellar spacing)의 정도 또는 $\beta$-Sn과 라멜라 조직 사이의 결정립계와 라멜라 조직 내 결정립계에서의 슬라이딩 모드(sliding mode) 변형 정도, 석출상의 크기와 분포 정도 등이 연신률 및 변형속도 민감도와 같은 연성 특성에 가장 큰 영향을 미치는 인자인 것으로 분석되었다.

• Journal of the Microelectronics and Packaging Society
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• v.14 no.3
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• pp.1-6
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• 2007

In this study, the pentacene thin films were prepared by the soluble process, and characterized fur the application of the organic thin film transistor(OTFT) device. To dissolve the pentacene material, two kinds of solvents such as toluene and chloroform were used, and the effects of these solvents on the properties of pentacene thin films coated on ITO/Glass substrate were investigated. Pentacene thin films were prepared by using spin-coating methode and characterized the surface morphology, crystalline and electrical properties. From the AFM measurement, the surface morphology of the pentacene film dissolved with chloroform was improved compared with the one dissolved with toluene solvent. XRD measurement showed that all prepared pentacene film samples were amorphous crystal phases without crystallization of the films. The electrical properties of the pentacene film dissolved with chloroform showed better results than the ones using toluene solvent by hall measurement system. The carrier concentration and the mobility values of pentacene films using chloroform solvent were found to be $-3.225{\times}10^{14}\;cm^{-3}$ and $3.5{\times}10^{-1}\;cm^2{\cdot}V^{-1}{\cdot}S^[-1}$, respectively. The resistivity was about $2.5{\times}10^2\;{\Omega}{\cdot}cm$.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.29 no.6
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• pp.345-351
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• 2019

Recently, ink-jet printing technology has been applied for various industries such as semiconductor, display, ceramic tile decoration. Ink-jet printing has advantages of high resolution patterning, fast printing speed, high ink efficiency and many attempts have been made to apply functional materials with excellent physical and chemical properties for the ink-jet printing process. Due to these advantages, research scope of ink-jet printing is expanding from conventional two-dimensional printing to three-dimensional printing. In order to expand the application of ink-jet printing, it is necessary to optimize the rheological properties of the ink and the interaction with the substrate. In this study, photo curable ceramic complex ink containing nano silica particles were synthesized and its printability was characterized. Contact angle of the photo curable silica ink were modified by control of the ink composition and the surface property of the substrate. Effects of contact angle on printing resolution and three-dimensional printability were investigated in detail.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.6
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• pp.39-47
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• 1998

A fourth-order $\Sigma$-$\Delta$ modulator is designed and implemented in 0.6 $\mu\textrm{m}$ CMOS technology. The modulator is verified by introducing nonlinear factors such as DC gain and slew rate in system model that determines the transfer function in S-domain and in time-domain. Dynamic range is more than 110 dB and the peak SM is 102.6 dB at a clock rate of 2.8224 MHz for voiceband signal. The structure of a ∑-$\Delta$ modulator is a modified fourth-order ∑-$\Delta$ modulator using direct feedback loop method, which improves performance and consumes less power. The transmission zero for noise is located in the first-second integrator loop, which reduces entire size of capacitors, reduces the active area of the chip, improves the performance, and reduces power dissipation. The system is stable because the output variation with respect to unit time is small compared with that of the third integrator. It is easy to implement because the size of the capacitor in the first integrator, and the size of the third integrator is small because we use the noise reduction technique. This paper represents a new design method by modeling that conceptually decides transfer function in S-domain and in Z-domain, determines the cutoff frequency of signal, maximizes signal power in each integrator, and decides optimal transmission-zero frequency for noise. The active area of the prototype chip is 5.25$\textrm{mm}^2$, and it dissipates 10 mW of power from a 5V supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.4
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• pp.60-70
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• 2000

An 8$\times$8+20-bit MAC is designed with low power design methodologies at each of the system design levels. At algorithm level, a new method for multipl $y_tract operation is proposed, and it saves the transistor counts over conventional methods in hardware realization. A new Booth selector circuit using NMOS pass-transistor logic is also proposed at circuit level. It is superior to other circuits designed by CMOS in power-delay-product. And at architecture level, we adopted an ELM adder that is known to be the most efficient in power consumption, operating frequency, area and design regularity as the final adder. For registers, dynamic CMOS single-edge triggered flip-flops are used because they need less transistors per bit. To increase the operating frequency 2-stage pipeline architecture is adopted, and fast 4：2 compressors are applied in Wallace tree block. As a simulation result, the designed MAC in 0.6${\mu}{\textrm}{m}$ 1-poly 3-metal CMOS process is operated at 200MHz, 3.3V and consumed 35㎽ of power in multiply operation, and operated at 100MHz consuming 29㎽ in MAC operations, respectively.ly.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.3
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• pp.7-17
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• 2010

In this paper, an innovative low-power SRAM based on 4-transistor latch cell is described. The memory cells are composed of two cross-coupled inverters without access transistors. The sources of PMOS transistors are connected to bitlines while the sources of NMOS transistors are connected to wordlines. They are accessed by totally new read and write method which results in low operating power dissipation in the nature. Moreover, the design reduces the leakage current in the memory cells. The proposed SRAM has been demonstrated through 16-kbit test chip fabricated in a 0.18-${\mu}m$ CMOS process. It shows 17.5 ns access at 1.8-V supply while consuming dynamic power of $87.6\;{\mu}W/MHz$ (for read cycle) and $70.2\;{\mu}W/MHz$ (for write cycle). Compared with those of the conventional 6-transistor SRAM, it exhibits the power reduction of 30 % (read) and 42 % (write) respectively. Silicon measurement also confirms that the proposed SRAM achieves nearly 64 % reduction in the total standby power dissipation. This novel SRAM might be effective in realizing low-power embedded memory in future mobile applications.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.10
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• pp.82-90
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• 2011

Because of the development of Smart phone devices, the demands of high performance FPU(Floating-point Unit) becomes increasing. Therefore, we propose the high-speed single-/double-precision FPU design that includes an elementary add/sub unit and improved multiplier and compare and convert units. The most commonly used add/sub unit is optimized by the parallel rounding unit. The matrix operation is used in complex calculation something like a graphic calculation. We designed the Multiply-Add Fused(MAF) instead of multiplier to calculate the matrix more quickly. The branch instruction that is decided by the compare operation is very frequently used in various programs. We bypassed the result of the compare operation before all the pipeline processes ended to decrease the total execution time. And we included additional convert operations that are added in IEEE754-2008 standard. To verify our RTL designs, we chose four hundred thousand test vectors by weighted random method and simulated each unit. The FPU that was synthesized by Samsung's 45-nm low-power process satisfied the 600-MHz operation frequency. And we confirm a reduction in area by comparing the improved FPU with the existing FPU.

• 대한공업교육학회지
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• v.34 no.1
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• pp.196-209
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• 2009

The purpose of this study was to analyze engineering basic competencies about the time completed a course and educational needs of engineering college graduates. Survey method using questionnaire was the major research method of this study. A survey of 807 engineering college graduates was carried out. Questionnaire were made of the level of engineering basic competencies of engineering college graduates, its priorities of actual vocation and level of engineering basic competencies of major. Major results of the study, some recommendations for future researches were made as follows: The level of engineering basic competencies of engineering college graduates was 3.3 average(5 full marks). Engineering basic competencies that educational needs were high respectively, were an ability to communicate effectively, an ability to design a system, component, or process to meet desired needs, an ability to function on multi-disciplinary teams, an ability to understand global culture and cooperate internationally, an ability to design and conduct experiment as well as to analyze and interpret data, and an ability to engage in life-long learning.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.18 no.10
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• pp.531-538
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• 2017

In the case of hydraulic pressure type fuse, we accept or reject certain product lots by considering the number of defective products in the operating pressure test. Generally, this procedure, known as 'The inspection by attributes', has been most commonly used in the field of quality assurance of products. However, the method of inspection by attributes suffers because it tests more samples than inspection by variables. Even though the quality of the products has remained stable in the process condition, the same number of samples is required for every lot, which wastes time and money. This paper suggests that the lot acceptance procedure is changed from inspection by attributes to inspection by variables. We can calculate the statistical tolerance percent of defectives and compare this to the Acceptable Quality Level (AQL) in order to save money and time. It is also easier to monitor and control the quality of products by using the process capability index and x-bar charts. In conclusion, the procedure delivers mutual benefit to both the customer and the producer by securing high quality products and reference data.