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Floating Point Unit Design for the IEEE754-2008  

Hwang, Jin-Ha (Department of Electrical and Electronic Engineering, Yonsei University)
Kim, Hyun-Pil (Department of Electrical and Electronic Engineering, Yonsei University)
Park, Sang-Su (Department of Electrical and Electronic Engineering, Yonsei University)
Lee, Yong-Surk (Department of Electrical and Electronic Engineering, Yonsei University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.48, no.10, 2011 , pp. 82-90 More about this Journal
Abstract
Because of the development of Smart phone devices, the demands of high performance FPU(Floating-point Unit) becomes increasing. Therefore, we propose the high-speed single-/double-precision FPU design that includes an elementary add/sub unit and improved multiplier and compare and convert units. The most commonly used add/sub unit is optimized by the parallel rounding unit. The matrix operation is used in complex calculation something like a graphic calculation. We designed the Multiply-Add Fused(MAF) instead of multiplier to calculate the matrix more quickly. The branch instruction that is decided by the compare operation is very frequently used in various programs. We bypassed the result of the compare operation before all the pipeline processes ended to decrease the total execution time. And we included additional convert operations that are added in IEEE754-2008 standard. To verify our RTL designs, we chose four hundred thousand test vectors by weighted random method and simulated each unit. The FPU that was synthesized by Samsung's 45-nm low-power process satisfied the 600-MHz operation frequency. And we confirm a reduction in area by comparing the improved FPU with the existing FPU.
Keywords
Floating-point Unit; Multiply-Add Fused; convertor; ALU; IEEE754-2008;
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