• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.2 s.332
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• pp.49-56
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• 2005

In this paper, we propose a memory BIST Circuit Creation System which creates BIST circuit based on user defined fault model and generates the optimized march test algorithm. Traditional tools have some limit that regenerates BIST circuit after changing the memory type or test algorithm. However, this proposed creation system can automatically generate memory BIST circuit which is suitable in the various memory type and apply algorithm which is required by user. And it gets more efficient through optimizing algorithms for fault models which is selected randomly according to proposed nile. In addition, it support various address width and data and consider interface of IEEE 1149.1 circuit.

• The Transactions of the Korea Information Processing Society
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• v.4 no.2
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• pp.395-400
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• 1997

An important quality characteristic of a software reliability.Software reliablilty growh models prvied the tools to evluate and moniter the reliabolty growth behavior of the sofwate during the testing phase Therefore failure data collected during the testing phase should be continmuosly analyzed on the basis of some selected software reliability growth models.For the cases where nonhomogeneous Poisson proxess models are the candiate models,we suggest Poisson regression model, which expresses the relationship between the expeted and actual failures counts in disjonint time intervals,for analyzing the failure count data.The weighted lest squares method is then used to-estimate the paramethers in the parameters in the model:The resulting estimators are equivalent to the maximum likelihood estimators. The method is illustrated by analyzing the failutr count data gathered from a large- scale switchong system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.10 s.340
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• pp.47-54
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• 2005

In this paper, a new synthesis method for testability of synchronous sequential circuits is suggested on an incompletely-specified state transition graph (STG) by reducing the number of redundant faults. In the suggested synthesis method, 1) a given STG is modified by adding undefined states and unspecified input transitions using distinguishable transition, 2) the STG is modified to be strongly-connected as much as possible. Experimental results with MCNC benchmark show that the number of redundant faults of gate-level circuits synthesized by our modified STGs are reduced, and much higher fault coverage is obtained.

• Proceedings of the Korea Inteligent Information System Society Conference
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• 2002.11a
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• pp.473-479
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• 2002

NHPP에 근거한 SRGM을 구성하는 새로운 안을 제시한다. 본 논문의 주요 초점은 소프트웨어 신뢰도모델링에서 효과적인 파라미터분해기법을 제공하는 것이다. 이는 테스트노력과 결함검출비를 동시에 고려하는 것이다. 일반적으로, 소프트웨어결함검출/제거메카니즘은 이전의 검출/제거결함과 테스트노력을 어떻게 활용하느냐에 달려있다. 실제 현장 연구로부터 우리는 테스트노력소모패턴을 추론하여 FDR의 경향을 예측할 수 있을 것으로 생각된다. 결함검출이 증가, 감소 및 일정한 것 등 광범위에 걸쳐서 나타나는 경향을 잡아내는 고유의 융통성을 가지는 하나의 시변수집합인 FDR모델에 근거한 테스트노력을 개발하였다. 이 스킴은 구조에 융통성이 있어서 여러 가지 테스트노력을 고려하여 광범위한 소프트웨어 개발 환경을 모델화할 수 있다 본 논문에서는 FDR을 기술하고, 관련된 테스트 행위를 이러한 새로운 모델링접근법에 연합시킬 수 있다. 우리의 모델과 그리고 이것과 관련된 파라미터 분해기법을 적용한 것을 여러 가지 소프트웨어 프로젝트에서 도출한 실제 데이터집합을 통하여 시연한다. 분석결과에 의하면 SRGM에 관한 테스트노력과 FDR을 결합하기 위한 제안된 구조가 상당히 정확한 예측능력을 보여주고 있으며, 실제 수명상황을 좀더 정대하게 설명해 준다. 이 기법은 광범위한 소프트웨어시스템에 쓰일 수 있다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.8
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• pp.610-618
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• 2003

Recently, many deterministic built-in self-test schemes to reduce test time have been researched. These schemes can achieve a good quality test by shortening the whole test process, but require complex algorithms or much hardware. In this paper, a new deterministic BIST scheme is provided that reduces the additional hardware requirements, as well as keeping test time to a minimum. The proposed BIST (Built-In Self-Test) methodology brings about the reduction of the hardware requirements for pseudo-random tests as well. Theoretical study demonstrates the possibility of reducing the hardware requirements for both pseudo-random and deterministic tests, with some explanations and examples. Experimental results show that in the proposed test scheme the hardware requirements for the pseudo-random test and deterministic test are less than in previous research.

• The KIPS Transactions:PartD
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• v.14D no.6
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• pp.649-656
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• 2007

Today, controller area network(CAN) is a field bus that is nowadays widespread in distributed embedded systems due to its electrical robustness, low price, and deterministic access delay. However, its use safety-critical applications has been controversial due to dependability limitation, such as those arising from its bus topology. Thus it is important to analyze the performance of the network in terms of load of data bus, maximum time delay, communication contention, and others during the design phase of the controller area network. In this paper, a simulation algorithm is introduced to evaluate the communication performance of the vehicle network and apply software base fault injection techniques. This can not only reduce any erratic implementation of the vehicle network but it also improves the reliability of the system.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.1
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• pp.131-136
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• 2013

TSV based 3D ICs have been widely developed with new problems at die and IC levels. It is imperative to test at post-bond as well as pre-bond to achieve high reliability and yield. This paper introduces a new testable design technique which not only test microscopic defects at TSV input/output contact at a die but also test interconnect defects at a stacked IC. IEEE 1500 wrapper cells are augmented and through at-speed tests for pre-bond die and post-bond IC, known-good-die and defect free 3D IC can be massively manufactured+.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.8
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• pp.18-24
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• 2011

A new problem happens with the evolution of TSV based 3D IC design. The bonding process takes place which follows with the testing of design for proper connectivity in the absence of TSV redundancy. In order to achieve good yield, the design should be tested with redundancy TSV. This paper presents a wrapper cell design for redundancy TSV interconnect test. The design for test technique, in terms of hardware and software perspectives is described. The wrapper cell with hardware design can use original test patterns. However, software design has less area overhead.

• Journal of the Institute of Convergence Signal Processing
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• v.12 no.3
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• pp.212-216
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• 2011

Fault detection technique for photovoltaic power systems is significant to dramatically reduce economic damage in industrial fields. This paper presents a novel fault detection approach using Fourier neural networks and stochastic decision making strategy for photovoltaic systems. We achieve neural modeling to represent its nonlinear dynamic behaviors through a gradient descent based learning algorithm. Next, a general likelihood ratio test (GLRT) is derived for constructing a decision malling mechanism in stochastic fault detection. A testbed of photovoltaic power systems is established to conduct real-time experiments in which the DC power line communication (DPLC) technique is employed to transfer data sets measured from the photovoltaic panels to PC systems. We demonstrate our proposed fault detection methodology is reliable and practicable over this real-time experiment.

• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.5
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• pp.666-673
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• 1986

This paper proposes a testable design method of PLA's with low overhead and high fault coverage for multiple faults. Only a shift register and control input of 2-bit decoder are used for extra hardware. By using a control input, the bit lines are controlled effectively. As the fault model, bridging faults and multiple faults of different fault models are particularly considered. 'Fault equivalence relation' and 'dominant faults' are defined to be used for detection of multiple faults. Also, an eadily testable folded PLA by this method is described.