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Synthesis for Testability of Synchronous Sequential Circuits Using Undefined States on Incompletely-Specified State Transition Graph  

Choi, Ho-Yong (School of Electrical and Computer Eng., Chungbuk National University)
Kim, Soo-Hyun (Samsung SDI Cop.)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.42, no.10, 2005 , pp. 47-54 More about this Journal
Abstract
In this paper, a new synthesis method for testability of synchronous sequential circuits is suggested on an incompletely-specified state transition graph (STG) by reducing the number of redundant faults. In the suggested synthesis method, 1) a given STG is modified by adding undefined states and unspecified input transitions using distinguishable transition, 2) the STG is modified to be strongly-connected as much as possible. Experimental results with MCNC benchmark show that the number of redundant faults of gate-level circuits synthesized by our modified STGs are reduced, and much higher fault coverage is obtained.
Keywords
synthesis for testability; undefined states; redundant faults; distinguishable transition;
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