Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
권호 표지

Synthesis for Testability of Synchronous Sequential Circuits Using Undefined States on Incompletely-Specified State Transition Graph

불완전명세 상태천이그래프상에서 미정의상태를 이용한 동기순차회로의 테스트용이화 합성

  • Published : 2005.10.01
Download PDF
⟨ Previous Next ⟩

Abstract

In this paper, a new synthesis method for testability of synchronous sequential circuits is suggested on an incompletely-specified state transition graph (STG) by reducing the number of redundant faults. In the suggested synthesis method, 1) a given STG is modified by adding undefined states and unspecified input transitions using distinguishable transition, 2) the STG is modified to be strongly-connected as much as possible. Experimental results with MCNC benchmark show that the number of redundant faults of gate-level circuits synthesized by our modified STGs are reduced, and much higher fault coverage is obtained.

본 논문에서는 불완전명세(incompletely-specified)를 가진 상태전이그래프(state transition graph: STG)상에서 리던던트 고장(redundant faults)수를 줄여 테스트를 용이하게 하기 위한 새로운 동기 순차회로의 합성방법을 제안한다. 이 STG 합성법에는 1) 구별전이(distinguishable transition)을 이용하여 무정의상태(undefined states)와 불완전명세된 입력전이를 추가하고, 2) 가능한 한 강연결(strongly-connected)이 되도록 하는 방법을 사용한다. 제안된 방법을 이용하여 MCNC 벤치마크 회로에 대해 실험한 결과, 대부분의 회로에 대해 무해 고장의 수가 현격히 줄어들어 높은 고장검출을 얻었다.

Keywords

References

  1. S. Devadas, H.-K. Tony Ma, A. R. Newton, and A. Sangiovanni-Vincentelli, 'Irredundant sequential machines via optimal logic synthesis,' IEEE Trans. on CAD, Vol. 9, pp. 8-18, Jan. 1990 https://doi.org/10.1109/43.45852
  2. I. Pomeranz and S. M. Reddy, 'Classification of faults in synchronous sequential circuits,' IEEE Trans. on Computer, Vol. 42, no. 9, Sep. 1993 https://doi.org/10.1109/12.241596
  3. S. M. Reddy, I. Pomeranz, X. Lin, and N. Basrurkan, 'New procedures for identifying undetectable and redundant faults in synchronous sequential circuits,' Proc. of VISI Test Symposium, pp. 275-281, 1999 https://doi.org/10.1109/VTEST.1999.766676
  4. D. E. Long, M. A. Iyer, and M. Abramovici, 'Identifying sequentially untestable faults using illegal states,' Proc. VLSI Test Symp., pp. 4-11, May 1995 https://doi.org/10.1109/VTEST.1995.512610
  5. K.-T. Cheng, 'On removing redundancy in sequential circuits,' Proc. of 28th Design Automation Conference, pp. 164-169, June 1991 https://doi.org/10.1145/127601.127655
  6. K.-T. Cheng, 'Redundancy removal for sequential circuits without reset states,' IEEE Trans. on CAD, Vol. 12, no. 1, Jan. 1993 https://doi.org/10.1109/43.184840
  7. X. Lin, I. Pomeranz, and S. M. Reddy, 'On finding undetectable and redundant faults in synchronous sequential circuits,' Proc. of Int'l. Conf. on Computer Design, Oct. 1998 https://doi.org/10.1109/ICCD.1998.727095
  8. T. E. Marchok, A. EI-Maleh, W, Maly, and J. Rajski, 'A complexity analysis of sequential A TPG,' IEEE Trans. on CAD, Vol. 15, no. 11, pp. 1409-1423, Nov. 1996 https://doi.org/10.1109/43.543773
  9. I. Pomeranz and S. M. Reddy, 'Design and Synthesis for Testability of Synchronous Sequential Circuits Based on Strong-Connectivity,' The 20th Int'l. Symp. on FTCS-23. Digest Papers., pp. 492-501, Aug. 1993 https://doi.org/10.1109/FTCS.1993.627352
  10. A. Ghosh, S. Devadas, and A. R. Newton, Sequential Logic Testing and Verification, Kluwer Academic Publishers, 1978
  11. E. M. Sentovich, K J. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldanha, H. Savoj, P. R. Stephan, R. K Brayton, and A. Sangiovanni-Vinventelli, 'SIS : A system for sequential circuit synthesis,' Electronics Research Laboratory Memorandum, no.UCB/ERL M92/41, 1992
  12. T. M. Niermann and J. H. Patel, 'HITEC : A test generation package for sequential circuits,' Proc. of EDAC, pp. 132-135, May 1994 https://doi.org/10.1109/EDAC.1991.206393