• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.11
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• pp.57-65
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• 2014

This paper presents a framework that is based on a reconfigurable macro-model of current-mode logic (CML) high-speed digital circuits enabling equation-based design optimization. The proposed macro-model is compatible with geometric programming, thereby enabling constraint-driven top-level power optimization. The proposed optimization framework is applied to a design of CML based serial-link transmitter with user-defined design specifications as an example of high speed digital circuits using 45nm and 90nm CMOS technology. The proposed optimization framework can derive a design with optimal power efficiency for given transistor technology nodes.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.10
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• pp.9-15
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• 2009

In this paper, we invented a new structure of fast ATC(Automatic Threshold Control) circuit. Using the structure we made a new burst-mode limiting amplifier with fast ATC function using commercial $0.8{\mu}m$ BiCMOS technology. It's ATC function worked so fast that even the first bit of burst-data could be detected, which confirmed that the new structure was useful for fast ATC. However, in the beginning of a burst, distortions in duty-cycle occurred and increased up to 59% of duty-cycle as amplitude of input signal increased. But we confirmed that after 10 cycles passed, duty-cycles was staying below 52% of duty-cycle for any magnitude of input signal.

• Journal of Korea Society of Industrial Information Systems
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• v.19 no.6
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• pp.1-6
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• 2014

The delay-insensitive Null Convention Logic (NCL) asynchronous design as one of innovative asynchronous logic design methodologies has many advantages of inherent robustness, power consumption, and easy design reuses. However, transistor-level structures of conventional NCL gate cells have weakness of low speed, high area overhead or high wire complexity. Therefore, this paper proposes a new high-speed NCL gate cells designed at transistor level for high-speed, low area overhead, and low wire complexity. The proposed NCL gate cells have been compared to the conventional NCL gates in terms of circuit delay, area and power consumption.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.12
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• pp.159-164
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• 2005

Recently, it has demanded high-speed digital circuits as information increase. Therefore, electromagnetic characteristics of compact microwave circuit occurred importantly. And, the effect of the imperfect ground plane on the signal integrity and influence of coupling between two parallel lines for high-speed digital transmission line on the printed circuit board is investigated by FDTD simulations in 3-D electromagnetic analysis method. The results of FDTD simulation are compared with the ADS simulation in commercial software, analyzed lumped element of modeling and electromagnetic wave's radiation of slot as frequency. As a consequence, when the slot in the ground plane is under microstrip line, it has much effect on propagation of wave.

• 발명특허
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• v.35 no.11
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• pp.32-41
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• 2010

• Proceedings of the Korea Information Processing Society Conference
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• 2005.05a
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• pp.1641-1644
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• 2005

현재의 인터넷과 같은 전자 통신망과 멀티미디어 시스템의 발달은 고속의 대용량 데이터 전송을 필요로 한다. 초고속 통신 시스템에서의 고속 데이터 전송은 주로 광섬유를 사용하는 광통신으로 이루어지고 있다. FTTH(Fiber To The Home)와 같은 광통신 시스템은 멀티미디어 커뮤니케이션을 위해 필요한 큰 데이터 전송률을 제공할 수 있기 때문에 더욱 더 중요성이 높아지고 있으며 이러한 광통신 시스템에서는 통신환경의 영향을 적게 받고 외부 조절이나 부품이 필요하지 않는 수신기 IC 의 개발이 요구되고 있다. 일반적으로 광통신 수신기에는 고속 동작에 적합한 특성을 가진 GaAs-MESFET 가 사용되고 있으나, 본 논문에서는 0.35um CMOS 2-poly 4-metal 공정을 이용하여 5Gbps 광수신기를 설계하였다. 설계된 수신기는 Preamplifier, Main amplifier, ABC 회로로 구성되어 있다. Transimpedance amplifier 형태의 Preamplifier 는 광검출기에 의해 생성된 전류 신호를 전압 신호로 변환한다. ABC 회로는 Peak_Hold 회로와 Bottom_Hold 회로로 구성되어 있다. 기존의 Peak_Hold 회로에서는 다이오드와 hold capacitor 를 이용하여 peak 값을 검출하도록 되어 있는데, 다이오드를 이용하는 경우 작은 입력 신호전압의 Peak 값을 검출하는 데 한계가 있다. 이러한 단점을 보완하고자 전류 거울형태의 Peak_Hold 회로를 설계하였다. 전류거울(current mirror)형태의 출력 신호의 duty error 를 줄이고 비트 에러율(Bit Error Rate)을 개선하는데 효과적이었다. 설계된 광수신기는 30dB 의 입력 dynamic range 와 입력 capacitance 3pF 에서 80MHz 의 대역폭을 가진다. 전력 소비량은 3.3V 전원 전압이 인가된 경우 약 150mW 정도이다.

• Proceedings of the Korea Contents Association Conference
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• 2007.11a
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• pp.825-828
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• 2007

오늘날 영상정보는 여러 분야에 있어 아주 큰 비중을 차지하고 있다. 다량의 정보를 가진 영상 신호의 효율적인 전송이나 저장에는 많은 제약이 따르게 되므로 고속의 영상 압축 관련 기술의 개발은 필수적이다. 본 논문은 JPEG에서 표준규격으로 채택하고 있는 DCT 및 양자화의 하드웨어에 적합한 고속연산 알고리즘을 연구하였고, JPEG 인코더에 적용 가능한 효율적인 회로 구조를 설계하였다. 연구된 DCT 및 양자화 모듈을 VHDL언어로 설계 및 합성하였으며 설계된 모듈은 영상 압축의 고속데이터 처리에 응용 가능하다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2018.10a
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• pp.507-511
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• 2018

This paper proposes a method for system development for high speed (300MHz) test of system IC semiconductors. The high-speed test system proposes a high-speed test circuit interface and a PCB design method for noise reduction. This paper proposes evaluation items and procedures for verifying the performance of the developed system. System IC The development of high speed test systems will help optimize the development of domestic system IC test equipment.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.11
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• pp.85-95
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• 2000

FIR digital filter is one of important blocks in DSP application. For more effective operation, lots of architecture are proposed. In our paper, we proposed a high speed FIR filter with area efficiency. To fast operation, we used transposed form filter as basic architecute. And, we used dual path registers line to wupport variation of filter operation, and filter cascade is also considered. To reduce area, we adopted truncated Booth multiplier to our filter design. As a result, we showed that filter area is reduced when filter optimization using of dual path registers line and truncated multiplier with same constraints againt previous method.

• Journal of Korean Electronics
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• v.4 no.8
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• pp.81-85
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• 1984