• Journal of the Korea Academia-Industrial cooperation Society
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• v.20 no.6
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• pp.14-18
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• 2019

The conductivity of a semiconductor is primarily determined by the carriers. To achieve higher conductivity, the number of carriers should be high, and an energy trap level is created so that the carriers can cross the forbidden zone with low energy. Carriers have a crystalline binding structure, and interfacial mismatching tends to make them less conductive. In general, high-concentration doping is typically used to increase mobility. However, higher conductivity is also observed in non-orthogonal conjugation structures. In this study, the phenomena of higher conductivity and higher mobility were observed with space charge limiting current due to tunneling phenomena, which are different from trapping phenomena. In an atypical structure, the number of carriers is low, the resistance is high, and the on/off characteristics of capacitances are improved, thus increasing the mobility. ZTO thin film improved the on/off characteristics of capacitances after heat treating at $150^{\circ}C$. In charging and discharging tests, there was a time difference in the charge and discharging shapes, there was no distinction between n and p type, and the bonding structure was amorphous, such as in the depletion layer. The amorphous bonding structure can be seen as a potential barrier, which is also a source of space charge limiting current and causes conduction as a result of tunneling. Thus, increased mobility was observed in the non-structured configuration, and the conductivity increased despite the reduction of carriers.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 2004.07a
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• pp.309-309
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• 2004

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.8
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• pp.555-559
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• 2003

In this paper, a new CMOS RF model for RF IC design including the capacitance effect, the skin effect, and the proximity effect between metal lines on the Si surface is proposed for tile first time for accurately predicting the RF behavior of CMOS devices. The capacitances between metal lines on the Si surface are modeled with the layout. And the skin effect is modeled with a parallel branch added in equivalent circuit of metal line. The proximity effect is modeled by adding the mutual inductance between cross-coupled inductances in the ladder circuit representation. Compared to the BSIM 3v3. the proposed RF model shows good agreements with the measured data and shows well the frequency dependent behavior of devices in GHz ranges.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.10
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• pp.1036-1043
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• 2003

In this paper, novel lumped equivalent circuits for a conventional parallel directional coupler are proposed. This novel equivalent circuits only have self inductance and self capacitance, so we can design exact lumped equivalent circuit. The equivalent circuit and design formula for the presented lumped element coupler is derived based on the even- and odd-mode properties of a parallel-coupled line. By using the derived design formula, we have designed the 3 dB and 10 dB lumped element directional couplers at the center frequency of 100 MHz and 2 GHz, respectively a chip type directional coupler has been designed with multilayer configurations by employing commercial EM simulator. Designed chip-type directional couplers have a 3 dB-coupling value at the center frequency of 2 GHz and fabricated lumped directional coupler on fr4 organic substrate has a 3 dB, 10 dB-coupling values at the center frequency of 100 MHz. Excellent agreements between simulation results and measurement results on the designed directional couplers show the validity of this paper. Furthermore, in order to adapt to multi-layer process such as Low Temperature Cofired Ceramic (LTCC), chip-type lumped element couplers have been designed by using this method.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.26 no.12
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• pp.1064-1071
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• 2015

In this paper, the electrical characteristics of interdigital capacitor with single-layer and multi-layer graphene were compared and analyzed in the microwave region. In equivalent circuit, a capacitor coupled with graphene showed the clear difference in electrical components such as resistance, inductance, and capacitance. In particular, for the capacitor with single-layer graphene, additional inductance and resistance occurred and the electrode resistance was also increased. Meanwhile, the self-resonance frequency of capacitor was shifted toward lower frequency region and its transmitted characteristic was considerably improved at frequency ranging from 0.4 to 4 GHz. The electrical characteristics of the capacitor with multi-layer graphene were somewhat different than the bare capacitor. In conclusion, we could confirm that single-layer graphene greatly influenced the electrical characteristics and performances of interdigital capacitor compared to multi-layer graphene.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.6
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• pp.548-553
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• 2004

In this paper, single, two, and three-section microstrip directional couplers are implemented for realizing the high directivity characteristics. The achievement of the high directivity with microstrip configuration is carried out by the distributed capacitor to decrease the even and odd mode phase difference. Capacitive compensation is performed by gap coupling of open stub formed in sub-coupled line. Therefore, insertion loss and power handling capability are not affected by the gap coupling. The proposed structure is easy to fabricate and incorporate another microwave device due to the planner microstrip. We designed and fabricated single, two, and three-section directional coupler with 20 ㏈ coupling. In spite of microstrip structure, the capacitive compensation structure shows 30 ㏈, 27 ㏈, and 25 ㏈ of directivity in single, two, and three-section directional couplers, respectively.

• Industry Promotion Research
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• v.3 no.1
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• pp.1-5
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• 2018

$SnO_2$ films were annealed in a vaccum atmosphere conditions to research the temperature dependency of current-voltage characteristics in according to the bonding structures. The $SnO_2$ film annealed in a vacuum became an amorphous structure but films annealed in an atmosphere condition had a crystal structure. The defects or depletion layer were formed by the electron-hole combination after annealing processes, and the electrical properties were changed depending on the crystal structure, binding energy and the variation of carriers. $SnO_2$ became more crystal-structural with increasing the annealing temperature, and the current increased at $SnO_2$ film annealed at $150^{\circ}C$ with Schottky current.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.2
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• pp.177-186
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• 2012

In this paper, we propose a design method that the crosstalk of probe connector pins satisfy the limitation of -30 dB. The parameters(inductance and capacitance) were extracted in the grid-structured probe connector pin system, and it is shown that the new parameters are easily calculated with increasing ground pin numbers using the previously calculated parameters. In addition, the crosstalk reduction algorithm by employing more grounds around the signal pin has been suggested, and it is confirmed that the suggested method is quite effective especially for the reduction of inductive couplings. Finally, we suggested the correlation between the pitch and the length of the pins to satisfy the crosstalk limitation of -30 dB with the given number of ground pins, which will be quite useful when design a probe connector pin system.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.37 no.8
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• pp.24-32
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• 2000

In this paper, we have designed and fabricated a new type power divider to be efficient to a size and electrical performance by folding each quarter-wavelength 70.7 Ω section into a tightly-coupled "meander-line" and inserting a slit. In this type, because of coupling, the electrical phase of quarter -wavelength line and the performance change. For this reason, with the inductive slit and the tuning of quarter-wavelength line length, we have compensated for those. The inductance value of the inserted slit is decided by its width and depth, therefore, we could improve the electrical performance through optimization of inductance. Input and output return losses of the designed power divider were -34.2 dB, -34.3 dB respectively, and isolation was -36.7 dB at 1.75 GHz. Besides, a new design approach reduced occupied substrate area by 3:1 approximately.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.05a
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• pp.154-156
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• 2016

In this paper, the proposed small size PLL works stable with the discrete loop filter which is controlled by voltage controlled oscillator's output signal. Sampling and a small size capacitor functioned negative feedback with switch does make it possible to integrate the PLL into a single chip. The proposed PLL is designed by 1.8V 0.18um CMOS process.