• Proceedings of the KIEE Conference
• /
• 2005.07c
• /
• pp.1847-1849
• /
• 2005

Unclamped Inductive Switching (UIS) 능력을 향상시키기 위하여 Floating p- well을 적용한 IGBT의 단락 회로 상태에서 과전압을 감지하는 새로운 보호회로를 제안하고 제작하였다. 실험 결과 제안된 회로는 fault 상황에서 fault 신호를 감지하고 즉시 게이트 전압을 낮추어 컬렉터 전류를 감소시켰다. 또한 Hard Switching Fault (HSF)와 Fault Under Load (FUL) 상황에서의 측정 및 2차원 Mixed-Mode 시뮬레이션을 통해 제안된 회로와 소자의 동작을 확인하였다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2022.05a
• /
• pp.481-482
• /
• 2022

In this paper, effect of random dopant fluctuation (RDF) of the top-transistor in a monolithic 3D inverter composed of MOSFET transistors is investigated with 3D TCAD simulation when the gate voltage of the bottom-transistor is changed. The sampling for investigating RDF effect was conducted through the kinetic monte carlo method, and the RDF effect on the threshold voltage variation in the top-transistor was investigated, and the electrical coupling between top-transistors and bottom-transistors was investigated.

• The Transactions of the Korea Information Processing Society
• /
• v.2 no.6
• /
• pp.879-890
• /
• 1995

This paper proposes the shuttle protocol that can gather management information from managed systems in an efficient way. In this paper, we implement the protocol and evaluate the performance by simulation. The major feature of the shuttle protocol is a chained logical connection through managed systems, and management informations to be collected are circulated among specified managed systems in circular order on a logical ring connection. The data generated by an managed system are relayed to a neighbor managed system and the system sends its data which has additional management information to received data. Finally, a manager stationman get all of data generated by every managed system. we will show the analysis of management traffic patterns using conventional polling schemes and the shuttle protocol implementation viable to TCP/IP network and improving existing polling mechansims. Additionally, it is performed to evaluate the packet processing time and its distribution of a manager system and a gateway, and the queue length of packet and bit length of gateway against conventional polling schemes by simulation using OPNRT, a simulation-dedicated package.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.24 no.7B
• /
• pp.1393-1399
• /
• 1999

In this paper, a VLSI design of the convolutional codec chip of code rate r=l/3, and constraint length K=9 is presented, which is able to correct errors of the received data when transmitted data is corrupted in channels. The circuit design mainly aimed for simple implementation. In the decoder, Viterbi algorithm with 3-bit soft-decision is employed. For information sequence updating and storage, the register exchange method is employed, where the register length is 5$\times$K(45 stages). The codec chip is designed using VHDL language and Design Analyzer and VHDL Simulator of Synopsys are used for simulation and synthesis. The chip is composed of ENCODER block, ALIGN block, BMC block, ACS block, SEL_MIN block and REG_EXCH block. The operation of the codec chip is verified though the logic simulations, where several error conditions are assumed. As a result of the timing simulation after synthesis, the decoding speed of 325.5Kbps is achieved, and 6,894 gates is used.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.43 no.4 s.346
• /
• pp.56-65
• /
• 2006

The Quantum-dot Cellular Automata (QCA) can be considered as a candidate for the next generation digital logic implementation technology due to their small feature sizes and ultra low power consumption. Up to now, several designs using Uh technology have been proposed. However, we found not all of the designs function properly. Furthermore, no general design guidelines have been proposed so far. A straightforward extension of a simple functional design pattern may fail. This makes designing a large scale circuits using QCA technology an extremely time-consuming process. In this paper, we show several critical vulnerabilities related to unbalanced input paths to QCA gates and sneak noise paths in QCA interconnect structures. In order to make up the vulnerabilities, a disciplinary guideline will be proposed. Also, we present a fast adder which has been designed by the discipline, and verified to be functional by the simulation.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.22 no.7
• /
• pp.949-955
• /
• 2018

Hardware-in-the-loop (HIL) simulation is a technique that can be employed for developing and testing complex real-time embedded systems. HIL simulation provides an effective platform for verifying power management system (PMS) performance of liquefied natural gas carriers, which are high value-added vessels such as offshore plants. However, HIL tests conducted by research institutes, including domestic shipyards, can be protracted. To address the said issue, this study proposes a field programmable gate array (FPGA) based PMS-HIL simulator that comprises a power supply, consumer, control console, and main switchboard. The proposed HIL simulation platform incorporated actual equipment data while conducting load sharing PMS tests. The proposed system was verified through symmetric, asymmetric, and fixed load sharing tests. The proposed system can thus potentially replace the standard factory acceptance tests. Furthermore, the proposed simulator can be helpful in developing additional systems for vessel automation and autonomous operation, including the development of energy management systems.

• Journal of KIISE
• /
• v.42 no.5
• /
• pp.621-628
• /
• 2015

The rapid growth of network technology makes the high-tech weapon. Thus, in the modern war, the ability to immediately use of the high-tech weapon is important. To realize this ability, continuous trainning is necessary but, this trainning spends many money. To improve the budget efficiency, Modeling and Simulation(M&S) are used. However, they seriously decrease the reality. Recently, the system which can support the combination of Live with Virtual simulation is on the rise. The typical example is L-V-C Environment and many kind of middleware which can support the L-V-C Envrionment are already proposed. Previous middleware can support the interoperability between different simulations but, it cannot completely interoperate three(Live, Virtual, Constructive) simulation environments. In this paper, to solve this problem, we propose the scheme which is combination between different middlewares. And we conduct the API mapping between HLA and DDS which are typical middleware and verify the scheme.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.14 no.3
• /
• pp.628-636
• /
• 2010

In this paper, we present a new type high speed parallel multiplier for performing the multiplication of two polynomials using standard basis in the finite fields GF($2^m$). Prior to construct the multiplier circuits, we design the basic cell of vector code generator(VCG) to perform the parallel multiplication of a multiplicand polynomial with a irreducible polynomial and design the partial product result cell(PPC) to generate the result of bit-parallel multiplication with one coefficient of a multiplicative polynomial with VCG circuits. The presented multiplier performs high speed parallel multiplication to connect PPC with VCG. The basic cell of VCG and PPC consists of one AND gate and one XOR gate respectively. Extending this process, we show the design of the generalized circuits for degree m and a simple example of constructing the multiplier circuit over finite fields GF($2^4$). Also, the presented multiplier is simulated by PSpice. The multiplier presented in this paper uses the VCGs and PPCS repeatedly, and is easy to extend the multiplication of two polynomials in the finite fields with very large degree m, and is suitable to VLSL.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.36 no.11A
• /
• pp.912-923
• /
• 2011

In this paper, we propose a routing protocol for WMNs to provide passengers in public transportation vehicles (e.g., bus and tram) with Internet access service. In order to support end users with a reliable Internet connection despite the mobility of vehicles, we assume that mesh router, called mobile mesh router (MMR), is installed in a vehicle and manages a route to Internet Gateway (IGW). We therefore propose an efficient routing protocol and its routing metric, called ETT-TR, considering trajectory information of vehicle as well as link quality in order to find a route between them. Using NS-2 simulations, we observe that our proposed routing protocol reduces the end-to-end delay and improves throughput performance.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.18 no.1
• /
• pp.135-141
• /
• 2014

In this paper, the device design guideline to reduce the threshold voltage variation with fin width in junctionless MuGFET has been suggested. It has been observed that the threshold voltage variation was increased with increase of fin width in junctionless MuGFETs. To reduce the threshold voltage variation with fin width in junctionless MuGFETs, 3-dimensional device simulation with different gate dielectric materials, silicon film thickness, and an optimized fin number has been performed. The simulation results showed that the threshold voltage variation can be reduced by the gate dielectric materials with a high dielectric constant such as $La_2O_3$ and the silicon film with ultra-thin thickness even though the fin width is increased. Particularly, the reduction of the threshold voltage variation and the subthreshold slope by reducing the fin width and increasing the fin numbers is known the optimized device design guideline in junctionless MuGFETs.