• The Journal of the Acoustical Society of Korea
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• v.40 no.2
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• pp.109-120
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• 2021

This paper proposes the H∞ norm based data association gate method to apply robustly the data association gate of passive sonar automatic target tracking which is on non-linear targets in dense cluttered environment. For target tracking, data association method selects the measurements within validated gate, which means validated measuring extent, as candidates for the data association. If the extent of the validated gate in the data association is not proper or the data association executes under dense cluttered environment, it is difficult to maintain the robustness of target tracking due to interference of clutter measurements. To resolve this problem, this paper proposes a novel gating method which applies H∞ norm based bisection algorithm combined with 3-σ gate method under Gaussian distribution assumption and tracking error covariance. The proposed method leads to alleviate the interference of clutters and to track the non-linear maneuvering target robustly. Through analytic method and simulation to utilize simulated data of horizontal and vertical bearing measurements, improvement of data association robustness is confirmed contrary to the conventional method.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.7 s.337
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• pp.5-12
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• 2005

The device performance of nano-scale center-channel (CC) double-gate (DG) MOSFET structure was investigated by numerically solving coupled Schr$\"{o}$dinger-Poisson and current continuity equations in a self-consistent manner. The CC operation and corresponding enhancement of current drive and transconductance of CC-NMOS are confirmed by comparing with the results of DG-NMOS which are performed under the condition of 10-80 nm gate length. Device optimization was theoretically performed in order to minimize the short-channel effects in terms of subthreshold swing, threshold voltage roll-off, and drain-induced barrier lowering. The simulation results indicate that DG-MOSFET structure including CC-NMOS is a promising candidates and quantum-mechanical modeling and simulation calculating the coupled Schr$\"{o}$dinger-Poisson and current continuity equations self-consistently are necessary for the application to sub-40 nm MOSFET technology.

• Asia-pacific Journal of Multimedia Services Convergent with Art, Humanities, and Sociology
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• v.8 no.6
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• pp.939-946
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• 2018

In this work, we present simple schematics for a three-terminal graphene-based nanoelectromechanical switch with the vertical electrode, and we investigated their operational dynamics via classical molecular dynamics simulations. The main structure is both the vertical pin electrode grown in the center of the square hole and the graphene covering on the hole. The potential difference between the bottom gate of the hole and the graphene of the top cover is applied to deflect the graphene. By performing classical molecular dynamic simulations, we investigate the nanoelectromechanical properties of a three-terminal graphene-based nanoelectromechanical switch with vertical pin electrode, which can be switched by the externally applied force. The elastostatic energy of the deflected graphene is also very important factor to analyze the three-terminal graphene-based nanoelectromechanical switch. This simulation work explicitly demonstrated that such devices are applicable to nanoscale sensors and quantum computing, as well as ultra-fast-response switching devices.

• Journal of Korean Society of Transportation
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• v.17 no.1
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• pp.159-171
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• 1999

This Paper aims to develop container terminal simulation models for medium and long term decision makings. It first undertakes in-depth survey of literature. finds its shortcomings and suggests some directions for improvement. It then proposes detailed design for the simulation models. Based on this it finally developes several simulation models and applies them to a hypothetical situation of a container terminal development. The results reveal that basic design questions such as length of quay, number of quay crane, size of storage area are well produced through the models.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.08a
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• pp.329-329
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• 2012

Mobile 기기로 둘러싸여있는 현대의 환경에서 Flash memory에 대한 중요성은 날로 더해가고 있다. Flash memory의 가격 경쟁력 강화와 사용되는 기기의 소형화를 위해 flash memory의 비례축소가 중요한 문제로 부각되고 있다. 그러나 다결정 실리콘을 플로팅 게이트로 이용하는planar flash memory 소자의 경우 비례 축소 시 short channel effect 와 leakage current, subthreshold swing의 증가로 인한 성능저하와 같은 문제들로 인해 한계에 다다르고 있다. 이를 해결하기 위해 CTF 메모리 소자, nanowire FET, FinFET과 같은 새로운 구조를 가지는 메모리소자에 대한 연구가 활발히 진행되고 있다. 본 연구에서는 22 nm 게이트 크기의 FinFET 구조를 가지는 플래시 메모리소자에서 fin의 두께와 높이의 변화에 따른 메모리 소자의 전기적 특성을 3-dimensional 구조에서 technology computer aided design ( TCAD ) tool을 이용하여 시뮬레이션 하였다. 본 연구에서는 3D FinFET 구조를 가진 플래시 메모리에 대한 시뮬레이션 하였다. FinFET 구조에서 채널영역은 planar 구조와 다르게 표면층이 multi-orientation을 가지므로 본 계산에서는 multi-orientation Lombardi mobility model을 이용하여 계산하였다. 계산에 사용된 FinFET flash memory 구조는 substrate의 도핑농도는 $1{\times}10^{18}$로 하였으며 source, drain, gate의 도핑농도는 $1{\times}10^{20}$으로 설정하여 계산하였다. Fin 높이는 28 nm로 고정한 상태에서 fin의 두께는 12 nm부터 28nm까지 6단계로 나누어서 각 구조에 대한 프로그램 특성과 전기적 특성을 관찰 하였다. 계산결과 FinFET 구조의 fin 두께가 두꺼워 질수록 채널형성이 늦어져 threshold voltage 값이 커지게 되고 subthreshold swing 값 또한 증가하여 전기적 특성이 나빠짐을 확인하였다. 각 구조에서의 전기장과 전기적 위치에너지의 분포가 fin의 두께에 따라 달라지므로써 이로 인해 프로그램 특성과 전기적 특성이 변화함을 확인하였다.

• The Journal of the Korea Contents Association
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• v.12 no.7
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• pp.11-20
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• 2012

This paper presents new instruction-level power model for an asynchronous processor, A8051. Even though the proposed model estimates power consumption as instruction level, this model reflects the behavioral features of asynchronous pipeline during the program is executed. Thus, it can effectively enhance the accuracy of power model for an asynchronous embedded processor without significant complexity of power model as well as the increase of simulation time. The proposed power model is based on the implementation of A8051 to reflect the characteristics of power consumption in A8051. The simulation results of the proposed model is compared with that of gate-level synthesized A8051. The proposed power model shows the accuracy of 94% and the simulation time for estimation the power consumption was reduced to 1,600 times.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.11a
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• pp.510-513
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• 2002

띠모양의 에미터와 에미터와 정렬된 띠모양의 케이트 구멍을 가진 탄소나노튜브(CNT) 삼극 구조에 대하여 전계방출 시뮬레이션을 수행하였다. 전자방출은 주로 가장자리에서 발생하였으며 에미터와 게이트사이의 간격이 가까워지면 급격히 증가하였다. 전자방출 특성도 상당히 우수하였다. 한쪽 가장자리만을 사용한 삼극구조의 경우에는 방출된 전자의 궤적이 좁은 띠모양으로 형성되어 방향성이 매우 우수하게 나타났다. 띠모양의 에미터 및 게이트로 이어진 삼극구조는 제작이 용이하고 조립할 때 정렬이 쉬운 장점이 있다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.12
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• pp.1-7
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• 2011

In this work, an analytical models for the threshold voltage and flat band voltage have been suggested and proved using 3-dimensional device simulator. The method for device design guideline and its example in nanowire junctionless transistor and example of device design of was also presented. One can find that the suggested model for threshold voltage and flat band voltage agrees with 3-dimension simulation results. The threshold voltage and flat band voltage are decreased with the increase of nanowire radius, gate oxide thickness, and channel impurity doping concentration. When the work function of gate material and the ratio of ON and OFF current is given, the device design guide line for nanowire junctionless transistor has been proposed. It is known that the device with high impurity channel concentration can be fabricated with th decreased of nanowire radius and gate oxide thickness.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.1
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• pp.1-10
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• 2003

Device characteristics of the Metal-Ferroclecric-Semiconductor FET(MFSFET) are simulated in this study. The field-dependent polarization model and the square-law FET model are employed in our simulation. C-V$_{G}$ curves generated from our MFSFET simulation exhibit the accumulation, the depletion and the inversion regions clearly. The capacitance, the subthreshold and the drain current characteristics as a function of gate bias exhibit the memory windows are 1 and 2 V, when the coercive voltages of ferroelectric are 0.5 and 1 V respectively. I$_{D}$-V$_{D}$ curves are composed of the triode and the saturation regions. The difference of saturation drain currents of the MFSFET device at the dual threshold voltages in I$_{D}$-V$_{D}$ curve is 1.5, 2.7, 4.0, and 5.7 ㎃, when the gate biases are 0, 0.1, 0.2 and 0.3V respectively. As the drain current is demonstrated after time delay, PLZT(10/30/70) thin film shows excellent reliability as well as the decrease of saturation current is about 18 % after 10 years. Our simulation model is expected to be very useful in the estimation of the behaviour of MFSFET devices.T devices.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.10a
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• pp.773-776
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• 2009

Last of the car industry can be grouped in one-vehicle electronic equipment, the development of the network, and accordingly the communication between each of the network is important. The network currently being used in vehicles include CAN, LIN, MOST, FlexRay, etc. are used. Network of several different kinds of applications using the federation said they were also germ, which causes the driver some more convenient environment, the desire to drive a vehicle that is increasing. If vehicle for other network environments with one integrated environment to make it a gateway for research done actively, the more applications are expected to be developed. In this paper, using gateway between CAN bus used for Body Train-side control of the vehicle network and MOST provided for infotainment systems. In vehicle automatic safety control system will be designed by One of CAN Nodes car speed information sending to MOST Navigation while don't received GPS information in the tunnel.