The Journal of the Korea Contents Association (한국콘텐츠학회논문지)

The Korea Contents Association (한국콘텐츠학회)
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Instruction-level Power Model for Asynchronous Processor, A8051

비동기식 프로세서 A8051의 명령어 레벨 소비 전력 모델

  • 이제훈 (강원대학교 삼척캠퍼스 공학대학 전자정보통신공학부)
  • Received : 2012.04.19
  • Accepted : 2012.06.08
  • Published : 2012.07.28
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Abstract

This paper presents new instruction-level power model for an asynchronous processor, A8051. Even though the proposed model estimates power consumption as instruction level, this model reflects the behavioral features of asynchronous pipeline during the program is executed. Thus, it can effectively enhance the accuracy of power model for an asynchronous embedded processor without significant complexity of power model as well as the increase of simulation time. The proposed power model is based on the implementation of A8051 to reflect the characteristics of power consumption in A8051. The simulation results of the proposed model is compared with that of gate-level synthesized A8051. The proposed power model shows the accuracy of 94% and the simulation time for estimation the power consumption was reduced to 1,600 times.

본 논문은 비동기식 프로세서, A8051의 명령어 레벨 소비 전력 모델을 제안한다. 제안된 소비 전력 모델은 명령어 레벨로 프로세서가 소비하는 전력을 예측하지만, 프로그램이 실행되는 동안 비동기식 파이프라인의 동작 특성을 반영한다. 따라서, 제안된 방법은 프로세서 소비 전력 모델의 복잡도와 시뮬레이션 시간의 증가 없이 비동기식 임베디드 프로세서 소비 전력 모델의 정확도를 효과적으로 향상시켰다. 제안된 소비 전력 모델은 A8051의 소비 전력 특성을 반영하여 구현되었고 게이트 레벨의 합성한 결과를 이용한 소비 전력 예측 결과와 비교하여 성능 평가를 수행하였다. 제안된 소비 전력 모델은 게이트 레벨의 소비 전력예측 결과와 비교하여 94%의 정확도를 보였고, 1,600 배 이상 시뮬레이션 시간을 단축하였다.

Keywords

References

  1. C. Y. Huang, Y. F. Yin, and C. J. Hsu, "SoC HW/SW verification and validation," Proc. of ASP-DAC 2011, pp.297-300, 2011.
  2. M. H. Wu, W. C. Lee, C. Y. Chuang, and S. Tsay, "Automatic generation of software TLM in multiple abstraction layers for efficient HW/SW co-simulation," Proc. of DATE 2010, pp.1177-1182, 2010.
  3. 류제천, 이제훈, 조경록, "멀티미디어 SoC용 시스템 버스의 소비 전력 모델링 및 해석", 한국콘텐츠학회논문지, 제7권, 제11호, pp.84-93, 2007(11). https://doi.org/10.5392/JKCA.2007.7.11.084
  4. V. Tiwari, D. Sinho, S. Rajgopal, G. Mehta, P. Patel, and F. Baez, "Reducing power in high-performance microprocessor," Proc. of the DAC 1998, pp.732-737, 1998.
  5. A. Efthymiou, Asynchronous techniques for power-adaptive processing, Ph.D Thesis, 2002.
  6. S. B. Furber, D. A. Edwards, and J. d. Garside, "AMULET3: a 100MIPS asynchronous embedded microprocessor," Proc. of ICCD 2000, pp.329-334, 2000.
  7. L. Clark, E. Hoffman, J. Miller, M. Biyani, Y. Liao, S. Strazdus, M. Morrow, K. Velarde, and M. Yarch, "An embedded 32-b microprocessor core for low-power and high-performance applications," IEEE Journal of Solid-State Circuits, Vol.36, No.11, pp.1599-1608, 2001(11). https://doi.org/10.1109/4.962279
  8. J. Warnock, "A 5.2GHz microprocessor chip for the IBM zEnterprizeTM system," Proc. of ISSCC 2011, pp.69-71, 2011.
  9. A. Efthymiou, J. D. Garside, and S. Temple, "A comparative power analysis of an asynchronous processor," Proc. of PATMOS'01, pp.1-10, 2001.
  10. Y. Shi, B. Gwee, and J. Cang, "Asynchronous DSP for low-power energy-efficient embedded systems," Microprocessors and Microsystems, Vol.35, No.3, pp.318-328, 2011(3). https://doi.org/10.1016/j.micpro.2011.02.001
  11. H. Jacobson, A. Buyuktosunoglu, P. Bose, E. Acar, and R. Eickemeyer, "Abstraction and microarchitecture scaling in early-stage power modeling," Proc. of HPCA2011, pp.394-405, 2011.
  12. A. Bink and R. York, "ARM966HS: The first licensable, clockless 32-bit processor core," IEEE Micro, Vol.27, No.2, pp.58-68, 2007(3).
  13. 이제훈, 조경록, "CISC 임베디드 컨트롤러를 위한 새로운 비동기 파이프라인 아키텍쳐, A8051," 대한전자공학회 논문지, 제40권 SD편, 제4호, pp.85-94, 2003(4).
  14. J. H. Lee, Y. H. Kim, and K. R. Cho, "Design of a fast asynchronous embedded CISC microprocessor, A8051," IEICE Trans. on Elec., Vol.E87-C, No.4, pp.527-534, 2004(4).
  15. J. H. Lee, Y. H Kim, and K. R. Cho, "A low-power implementation of asynchronous 8051 employing adaptive pipeline structure," IEEE T. on Circuits and Systems II-Express Briefs, Vol.55, No.7, pp.673-677, 2008(7). https://doi.org/10.1109/TCSII.2008.921589
  16. V. Tiwari, S. Malik, and A. Wolfe, "Power analysis of embedded system; A first step towards software power minimization," IEEE Trans. on VLSI, Vol.2, No.4, pp.437-445, 1994(4). https://doi.org/10.1109/92.335012
  17. Y. H. Park, S. Pasricha, F. Kurdahi, and N. Dutt, "Methodology for multi-granularity embedded processor power model generation for an ESL design flow," Proc. of CODES+ISSS 2008, pp.255-260, 2008.
  18. D. Brooks, V. Tiwari, and M. Martonosi, "Wattch: A framework for architectural-level power analysis and optimizations," Proc. of ISCA, pp.83-94, 2000
  19. W. Ye, N. Vijaykrishnan, M. Kandemir, and M. J. Irwin, "The design and use of SimplePower: A cycle-accurate energy estimation tool," Proc. of DAC 2000, pp.340-345, 2000.
  20. C. H. Geotys and R. J. Gebotysu, "An empirical comparison of algorithmic, instruction, and architectural power prediction model for high-performance embedded DSP processors, Proc. ISLPED, pp.121-123, 1998.