Browse > Article
http://dx.doi.org/10.5392/JKCA.2012.12.07.011

Instruction-level Power Model for Asynchronous Processor, A8051  

Lee, Je-Hoon (강원대학교 삼척캠퍼스 공학대학 전자정보통신공학부)
Publication Information
The Journal of the Korea Contents Association / v.12, no.7, 2012 , pp. 11-20 More about this Journal
Abstract
This paper presents new instruction-level power model for an asynchronous processor, A8051. Even though the proposed model estimates power consumption as instruction level, this model reflects the behavioral features of asynchronous pipeline during the program is executed. Thus, it can effectively enhance the accuracy of power model for an asynchronous embedded processor without significant complexity of power model as well as the increase of simulation time. The proposed power model is based on the implementation of A8051 to reflect the characteristics of power consumption in A8051. The simulation results of the proposed model is compared with that of gate-level synthesized A8051. The proposed power model shows the accuracy of 94% and the simulation time for estimation the power consumption was reduced to 1,600 times.
Keywords
Asynchronous Processor; Power Model; Power Estimation; System-on-chip;
Citations & Related Records
Times Cited By KSCI : 2  (Citation Analysis)
연도 인용수 순위
1 J. H. Lee, Y. H. Kim, and K. R. Cho, "Design of a fast asynchronous embedded CISC microprocessor, A8051," IEICE Trans. on Elec., Vol.E87-C, No.4, pp.527-534, 2004(4).
2 J. H. Lee, Y. H Kim, and K. R. Cho, "A low-power implementation of asynchronous 8051 employing adaptive pipeline structure," IEEE T. on Circuits and Systems II-Express Briefs, Vol.55, No.7, pp.673-677, 2008(7).   DOI   ScienceOn
3 V. Tiwari, S. Malik, and A. Wolfe, "Power analysis of embedded system; A first step towards software power minimization," IEEE Trans. on VLSI, Vol.2, No.4, pp.437-445, 1994(4).   DOI   ScienceOn
4 Y. H. Park, S. Pasricha, F. Kurdahi, and N. Dutt, "Methodology for multi-granularity embedded processor power model generation for an ESL design flow," Proc. of CODES+ISSS 2008, pp.255-260, 2008.
5 D. Brooks, V. Tiwari, and M. Martonosi, "Wattch: A framework for architectural-level power analysis and optimizations," Proc. of ISCA, pp.83-94, 2000
6 W. Ye, N. Vijaykrishnan, M. Kandemir, and M. J. Irwin, "The design and use of SimplePower: A cycle-accurate energy estimation tool," Proc. of DAC 2000, pp.340-345, 2000.
7 C. H. Geotys and R. J. Gebotysu, "An empirical comparison of algorithmic, instruction, and architectural power prediction model for high-performance embedded DSP processors, Proc. ISLPED, pp.121-123, 1998.
8 류제천, 이제훈, 조경록, "멀티미디어 SoC용 시스템 버스의 소비 전력 모델링 및 해석", 한국콘텐츠학회논문지, 제7권, 제11호, pp.84-93, 2007(11).   과학기술학회마을   DOI
9 V. Tiwari, D. Sinho, S. Rajgopal, G. Mehta, P. Patel, and F. Baez, "Reducing power in high-performance microprocessor," Proc. of the DAC 1998, pp.732-737, 1998.
10 A. Efthymiou, Asynchronous techniques for power-adaptive processing, Ph.D Thesis, 2002.
11 S. B. Furber, D. A. Edwards, and J. d. Garside, "AMULET3: a 100MIPS asynchronous embedded microprocessor," Proc. of ICCD 2000, pp.329-334, 2000.
12 L. Clark, E. Hoffman, J. Miller, M. Biyani, Y. Liao, S. Strazdus, M. Morrow, K. Velarde, and M. Yarch, "An embedded 32-b microprocessor core for low-power and high-performance applications," IEEE Journal of Solid-State Circuits, Vol.36, No.11, pp.1599-1608, 2001(11).   DOI   ScienceOn
13 J. Warnock, "A 5.2GHz microprocessor chip for the IBM zEnterprizeTM system," Proc. of ISSCC 2011, pp.69-71, 2011.
14 A. Bink and R. York, "ARM966HS: The first licensable, clockless 32-bit processor core," IEEE Micro, Vol.27, No.2, pp.58-68, 2007(3).
15 A. Efthymiou, J. D. Garside, and S. Temple, "A comparative power analysis of an asynchronous processor," Proc. of PATMOS'01, pp.1-10, 2001.
16 Y. Shi, B. Gwee, and J. Cang, "Asynchronous DSP for low-power energy-efficient embedded systems," Microprocessors and Microsystems, Vol.35, No.3, pp.318-328, 2011(3).   DOI   ScienceOn
17 H. Jacobson, A. Buyuktosunoglu, P. Bose, E. Acar, and R. Eickemeyer, "Abstraction and microarchitecture scaling in early-stage power modeling," Proc. of HPCA2011, pp.394-405, 2011.
18 이제훈, 조경록, "CISC 임베디드 컨트롤러를 위한 새로운 비동기 파이프라인 아키텍쳐, A8051," 대한전자공학회 논문지, 제40권 SD편, 제4호, pp.85-94, 2003(4).   과학기술학회마을
19 M. H. Wu, W. C. Lee, C. Y. Chuang, and S. Tsay, "Automatic generation of software TLM in multiple abstraction layers for efficient HW/SW co-simulation," Proc. of DATE 2010, pp.1177-1182, 2010.
20 C. Y. Huang, Y. F. Yin, and C. J. Hsu, "SoC HW/SW verification and validation," Proc. of ASP-DAC 2011, pp.297-300, 2011.