• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.2
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• pp.117-123
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• 2004

A 30 nm $In_{0.7}GaAs$ High Electron Mobility Transistor (HEMT) with triple-gate has been successfully fabricated using the $SiO_2/SiN_x$ sidewall process and BCB planarization. The sidewall gate process was used to obtain finer lines, and the width of the initial line could be lessened to half by this process. To fill the Schottky metal effectively to a narrow gate line after applying the developed sidewall process, the sputtered tungsten (W) metal was utilized instead of conventional e-beam evaporated metal. To reduce the parasitic capacitance through dielectric layers and the gate metal resistance ($R_g$), the etchedback BCB with a low dielectric constant was used as the supporting layer of a wide gate head, which also offered extremely low Rg of 1.7 Ohm for a total gate width ($W_g$) of 2x100m. The fabricated 30nm $In_{0.7}GaAs$ HEMTs showed $V_{th}$of -0.4V, $G_{m,max}$ of 1.7S/mm, and $f_T$ of 421GHz. These results indicate that InGaAs nano-HEMT with excellent device performance could be successfully fabricated through a reproducible and damage-free sidewall process without the aid of state-of-the-art lithography equipment. We also believe that the developed process will be directly applicable to the fabrication of deep sub-50nm InGaAs HEMTs if the initial line length can be reduced to below 50nm order.

• Korean Journal of Materials Research
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• v.9 no.5
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• pp.460-466
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• 1999

The deep level electron traps in AP-MOCVD GaAs/undoped Al\ulcornerGa\ulcornerAs/n-type GaAs heterostructures have been investigated by means of Deep Level Transient Spectroscopy DLTS). In terms of the experimental procedure, GaAs/undoped Al\ulcornerGa\ulcornerAs/n-type GaAs heterostructures were deposited on 2" undoped semi-insulating GaAs wafers by the AP-MOCVD method at $650^{\circ}C$ with TMGa, AsH3, TMAl, and SiH4 gases. The n-type GaAs conduction layers were doped with Si to the target concentration of about 2$\times$10\ulcornercm\ulcorner. The Al content was targeted to x=0.5 and the thicknesses of Al\ulcornerGa\ulcornerAs layers were targeted from 0 to 40 nm. In order to investigate the electrical characteristics, an array of Schottky diodes was built on the heterostructures by the lift-off process and Al thermal evaporation. Among the key results of this experiment, the deep level electron traps at 0.742~0.777 eV and 0.359~0.680 eV were observed in the heterostructures; however, only a 0.787 eV level was detected in n-type GaAs samples without the Al\ulcornerGa\ulcornerAs overlayer. It may be concluded that the 0.787 eV level is an EL2 level and that the 0.742~0.777 eV levels are related to EL2 and residual oxygen impurities which are usually found in MOCVD GaAs and Al\ulcornerGa\ulcornerAs materials grown at $630~660^{\circ}C$. The 0.359~0.680 eV levels may be due to the defects related with the al-O complex and residual Si impurities which are also usually known to exist in the MOCVD materials. Particularly, as the Si doping concentration in the n-type GaAs layer increased, the electron trap concentrations in the heterostructure materials and the magnitude of the C-V hysteresis in the Schottky diodes also increased, indicating that all are intimately related.ated.

• Korean Journal of Materials Research
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• v.22 no.4
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• pp.202-206
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• 2012

$CoSi_2$ was formed through annealing of atomic layer deposition Co thin films. Co ALD was carried out using bis(N,N'-diisopropylacetamidinato) cobalt ($Co(iPr-AMD)_2$) as a precursor and $NH_3$ as a reactant; this reaction produced a highly conformal Co film with low resistivity ($50\;{\mu}{\Omega}cm$). To prevent oxygen contamination, $ex-situ$ sputtered Ti and $in-situ$ ALD Ru were used as capping layers, and the silicide formation prepared by rapid thermal annealing (RTA) was used for comparison. Ru ALD was carried out with (Dimethylcyclopendienyl)(Ethylcyclopentadienyl) Ruthenium ((DMPD)(EtCp)Ru) and $O_2$ as a precursor and reactant, respectively; the resulting material has good conformality of as much as 90% in structure of high aspect ratio. X-ray diffraction showed that $CoSi_2$ was in a poly-crystalline state and formed at over $800^{\circ}C$ of annealing temperature for both cases. To investigate the as-deposited and annealed sample with each capping layer, high resolution scanning transmission electron microscopy (STEM) was employed with electron energy loss spectroscopy (EELS). After annealing, in the case of the Ti capping layer, $CoSi_2$ about 40 nm thick was formed while the $SiO_x$ interlayer, which is the native oxide, became thinner due to oxygen scavenging property of Ti. Although Si diffusion toward the outside occurred in the Ru capping layer case, and the Ru layer was not as good as the sputtered Ti layer, in terms of the lack of scavenging oxygen, the Ru layer prepared by the ALD process, with high conformality, acted as a capping layer, resulting in the prevention of oxidation and the formation of $CoSi_2$.

• ETRI Journal
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• v.35 no.3
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• pp.425-430
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• 2013

In this paper, we propose a triple-gate trench power MOSFET (TGRMOS) that is made through a modified RESURF stepped oxide (RSO) process, that is, the nitride_RSO process. The electrical characteristics of TGRMOSs, such as the blocking voltage ($BV_{DS}$) and on-state current ($I_{D,MAX}$), are strongly dependent on the gate configuration and its bias condition. In the nitride_RSO process, the thick single insulation layer ($SiO_2$) of a conventional RSO power MOSFET is changed to a multilayered insulator ($SiO_2/SiN_x/TEOS$). The inserted $SiN_x$ layer can create the selective etching of the TEOS layer between the gate oxide and poly-Si layers. After additional oxidation and the poly-Si filling processes, the gates are automatically separated into three parts. Moreover, to confirm the variation in the electrical properties of TGRMOSs, such as $BV_{DS}$ and $I_{D,MAX}$, simulation studies are performed on the function of the gate configurations and their bias conditions. $BV_{DS}$ and $I_{D,MAX}$ are controlled from 87 V to 152 V and from 0.14 mA to 0.24 mA at a 15-V gate voltage. This $I_{D,MAX}$ variation indicates the specific on-resistance modulation.

• Journal of Surface Science and Engineering
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• v.38 no.2
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• pp.65-68
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• 2005

The effect of crystal orientation and microstructure on the mechanical properties of $TaN_x$ was investigated. $TaN_x$ films were grown on $SiO_2$ substrates by ultrahigh vacuum unbalanced magnetron sputter deposition in mixed $Ar/N_2$ discharges at 20 mTorr (2.67 Pa) and at $350^{\circ}C$. Unlike the Ti-N system, in which TiN is the terminal phase, a large number of N-rich phases in the Ta-N system could lead to layers which had nano-sized lamella structure of coherent cubic and hexagonal phases, with a correct choice of nitrogen fraction in the sputtering mixture and ion irradiation energy during growth. The preferred orientations and the micro-structure of $TaN_x$ layers were controlled by varing incident ion energy $E_i\;(=30eV\~50eV)$ and nitrogen fractions $f_{N2}\;(=0.1\~0.15)$. $TaN_x$ layers were grown on (0002)-Ti underlayer as a crystallographic template in order to relieve the stress on the films. The structure of the $TaN_x$ film transformed from Bl-NaCl $\delta-TaN_x$ to lamellar structured Bl-NaCl $\delta-TaN_x$ + hexagonal $\varepsilon-TaN_x$ or Bl-NaCl $\delta-TaN_x$ + hexagonal $\gamma-TaN_x$ with increasing the ion energy at the same nitrogen fraction $f_{N2}$. The hardness of the films also increased by the structural change. At the nitrogen fraction of $0.1\~0.125$, the structure of the $TaN_x$ films was changed from $\delta-TaN_x\;+\;\varepsilon-TaN_x\;to\;\delta-TaN_x\;+\;\gamma-TaN_x$ with increasing the ion energy. However, at the nitrogen fraction of 0.15 the film structure did not change from $\delta-TaN_x\;+\;\varepsilon-TaN_x$ over the whole range of the applied ion energy. The hardness increased significantly from 21.1 GPa to 45.5 GPa with increasing the ion energy.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.23 no.3
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• pp.177-182
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• 2010

The pentacene-based organic thin film transistors(OTFTs) using polyvinylalcohol(PVA) alignment layer were fabricated on the $SiO_2$ evaporated to n-type (111) Si substrates. The pentacene film was deposited by thermally evaporated at $10^{-7}$ torr. X-ray diffraction (XRD) and atomic force microscope(AFM) measurement showed pentacene film which deposited on rubbed PVA layers were partially crystallized at (001) plane. The pentacene OTFTs with PVA layers rubbed perpendicular to the direction of current flow was shown to align better orientation than parallel rubbed case and thus to enhance the mobility and saturation current by a factor of 2.3 respectively. We obtained mobility by 0.026 $cm^2$/Vs and on-off current ratio by ${\sim}10^8$.

• Korean Journal of Materials Research
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• v.32 no.6
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• pp.293-300
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• 2022

This study investigated a graded-refractive-index (GRIN) coating pattern capable of improving the light extraction efficiency of GaN light-emitting diodes (LEDs). The planar LEDs had total internal reflection thanks to the large difference in refractive index between the LED semiconductor and the surrounding medium (air). The main goal of this paper was to reduce the trapped light inside the LED by controlling the refractive index using various compositions of (TiO₂)_x(SiO₂)_1-x in GRIN LEDs consisting of five dielectric layers. Several types of multilayer LEDs were simulated and it was determined the transmittance value of the LEDs with many layers was greater than the LEDs with less layers. Then, the specific ranges of incident angles of the individual layers which depend on the refractive index were evaluated. According to theoretical calculations, the light extraction efficiency (LEE) of the five-layer GRIN is 25.29 %, 28.54 % and 30.22 %, respectively. Consequently, the five-layer GRIN LEDs patterned enhancement outcome LEE over the reference planar LEDs. The results suggest the increased light extraction efficiency is related to the loss of Fresnel transmission and the release of the light mode trapped inside the LED chip by the graded-refractive-index.

• Journal of the Korean Magnetics Society
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• v.5 no.1
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• pp.42-47
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• 1995

FeN thin films for inductive recording heads were sputter deposited using RF diode sputtering mehtod from a pure iron target onto 7059 glass substrates, and their magnetic properties were measured. The magnetic properties were greatly affected by film thickness, gas pressure, sputter power and flow ratio of $N_{2}$ to Ar. Single layer FeN films with their thickness varied from $1,000\;{\AA}$ to $6,000\;{\AA}$ were doposited. 800 W sputter power, 3 mT gas pressure, $N_{2}$ to Ar flow ratio of 6.6 : 100 were the sputtering conditions. Up to 7 layers of FeN films having total thickness of $6,000\;{\AA}$ were deposited using $SiO_{2}$ of $30\;{\AA}$ thickness as intermediate layers and their coercivity and saturation magnetization were measured. The sputtering conditions were the same as those in the single layer films. Easy axis coercivity of the single layer FeN films gradually decreased as their thickness was increased, but for the films with their thicknesses above $3,000\;{\AA}$, the coercivity changed very little. As the number of the FeN layers were increased, the coercivity decreased We estimated the grain size of FeN films from the FWHM (Full Width at Half Maximum) of X-ray diffraction peaks. The grain size steadily decreased from about $200\;{\AA}$ to $120\;{\AA}$ as the number of layers were increased. Minimum hard axis coercivity of 0.4 Oe was obtained when the number of layers was four. Maximum relative permeability was 2,900 when the number of layers was three. The cut off frequeocy of the multilayer films were above 100 MHz.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.5B
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• pp.985-991
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• 2000

In this paper, the optimum structure of 2GHz magnetic thin film planar inductor were designed and fabricated to reduce the inductor area and to maximize the inductance L and quality factor Q of the inductor. The optimum design was performed utilizing Co90Fe10 layer multilayered with SiO2 layers to avoid the eddy-current skin effect and considering new lumped element model. New magnetic thin film inductors operating at 2GHz were fabricated on a Si substrate utilizing photo-lithography and lift-off techniques. The frequency characteristics of L, Q, and impedance in more than fifty identical inductors were measured using an RF Impedance Analyzer(HP4291B with HP16193A test fixture). The self-resonant frequencies(SRF) of the inductors were measured by a Vector Network Analyzer(HP8510). The developed inductors have SRF of 1.8 to 2.3GHz, L of 47 to 68nH, and Q of 70 to 80 near 1GHz. Finally, high frequency, high performance, planar micro-inductor(area=30.8 x 30.8il$^2$) with maximized L and Q were fabricated succefully.

• Korean Journal of Materials Research
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• v.11 no.3
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• pp.215-220
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• 2001

Amorphous Ti-Si-N films of approximately 200 and 650 thickness were reactively sputtered on Si wafers using a dc magnetron sputtering system at various $N_2$/Ar flow ratios. Their barrier properties between Cu (750 ) and Si were investigated by using sheet resistance measurements, XRD, SEM, RBS, and AES depth profiling focused on the effect of the nitrogen content in Ti-Si-N thin film on the Ti-Si-N barrier properties. As the nitrogen content increases, first the failure temperature tends to increase up to 46 % and then decrease. Barrier failure seems to occur by the diffusion of Cu into the Si substrate to form Cu$_3$Si, since no other X- ray diffraction intensity peak (for example, that for titanium silicide) than Cu and Cu$_3$Si Peaks appears up to 80$0^{\circ}C$. The optimal composition of Ti-Si-N in this study is $Ti_{29}$Si$_{25}$N$_{46}$. The failure temperatures of the $Ti_{29}$Si$_{25}$N$_{465}$ barrier layers 200 and 650 thick are 650 and $700^{\circ}C$, respectively.ely.