• Proceedings of the KIEE Conference
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• 1994.07b
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• pp.1223-1225
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• 1994

The properties of $TiN/TiSi_2$ bilayer formed by a rapid thermal anneal ing is investigated when thin $SiO_2$ film exists at the Ti-Si interface. The competitive reaction for the $TiN/TiSi_2$ bilayer occurs above $600^{\circ}C$. The thickness of the $TiSi_2$ layer decreases with increasing $SiO_2$ film thickness while the TiN layer increases at the competitive reaction. The composition of TiN layer is changed to the $TiN_xO_y$ film due to the thin $SiO_2$ layer at the Ti-Si interface while the structure of the TiN and $TiSi_2$ layers was not changed.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.29 no.6
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• pp.321-326
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• 2016

Minimizing the carrier recombination and electrical loss through surface passivation is required for high efficiency c-Si solar cell. Usually, $SiN_X$, $SiO_X$, $SiON_X$ and $AlO_X$ layers are used as passivation layer in solar cell application. Silicon oxide layer is one of the good passivation layer in Si based solar cell application. It has good selective carrier, low interface state density, good thermal stability and tunneling effect. Recently tunneling based passivation layer is used for high efficiency Si solar cell such as HIT, TOPCon and TRIEX structure. In this paper, we focused on silicon oxide grown by various the method (thermal, wet-chemical, plasma) and passivation effect in c-Si solar cell.

• Current Applied Physics
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• v.18 no.11
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• pp.1268-1274
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• 2018

We have investigated the effects of chemical rounding (CR) on the surface passivation and/or antireflection performance of $AlO_{x^-}$ and $AlO_x/SiN_x:H$ stack-passivated pyramid textured $p^+$-emitters with two different boron doping concentrations, and on the performance of bifacial n-PERT Si solar cells with a front pyramid textured $p^+$-emitter. From experimental results, we found that chemical rounding markedly enhances the passivation performance of $AlO_x$ layers on pyramid textured $p^+$-emitters, and the level of performance enhancement strongly depends on boron doping concentration. Meanwhile, chemical rounding increases solar-weighted reflectance ($R_{SW}$) from ~2.5 to ~3.7% for the $AlO_x/SiN_x:H$ stack-passivated pyramid textured $p^+$-emitters after 200-sec chemical rounding. Consequently, compared to non-rounded bifacial n-PERT Si cells, the short circuit current density Jsc of 200-sec-rounded bifacial n-PERT Si cells with ~60 and ${\sim}100{\Omega}/sq$ $p^+$-emitters is reduced by 0.8 and $0.6mA/cm^2$, respectively under front $p^+$-emitter side illumination. However, the loss in the short circuit current density Jsc is fully offset by the increased fill factor FF by 0.8 and 1.5% for the 200-sec-rounded cells with ~60 and ${\im}100{\Omega}/sq$ $p^+$-emitters, respectively. In particular, the cell efficiency of the 200-sec-rounded cells with a ${\sim}100{\Omega}/sq$ $p^+$-emitter is enhanced as a result, compared to that of the non-rounded cells. Based on our results, it could be expected that the cell efficiency of bifacial n-PERT Si cells would be improved without additional complicated and costly processes if chemical rounding and boron doping processes can be properly optimized.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.19-19
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• 2009

TiNxOy/TiNx multilayer thin films with a high resistance (~ k$Omega$) were deposited on SiO2/Si substrates at room temperature by sputtering. The TiNx thin films show island and smooth surface morphology in samples prepared by dc and rf magnetron sputtering, respectively. TiNxOy/TiNx multilayer has been developed to control temperature coefficient of resistance (TCR) by the incorporation of TiNx layer (positive TCR) inserted into TiNxOy layers(negative TCR). Electrical and structural properties of sputtered TiNxOy/TiNx multilayer films were investigated as a function of annealing temperature. In order to achieve a stable high resistivity, multilayer films were annealed at various temperatures in oxygen ambient. Samples annealed at 700 oC for 1 min exhibit a good TCR value and a stable high resistivity.

• Proceedings of the Korean Vacuum Society Conference
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• 2000.02a
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• pp.26-26
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• 2000

High quality epitaxial Y2O3 thin films were prepared on Si(111) and (001) substaretes by using ion beam assisted deposition. As a substrate, clean and chemically oxidized Si wafers were used and the effects of surface state on the film crystallinity were investigated. The crystalline quality of the films were estimated by x-ray scattering, rutherford backscattering spectroscopy/channeling, and high-resolution transmission electron microscopy (HRTEM). The interaction between Y and Si atoms interfere the nucleation of Y2O3 at the initial growth stage, it could be suppressed by the interface SiO2 layer. Therefore, SiO2 layer of the 4-6 layers, which have been known for hindering the crystal growth, could rather enhance the nucleation of the Y2O3 , and the high quality epitaxial film could be grown successfully. Electrical properties of Y2O3 films on Si(001) were measured by C-V and I-V, which revealed that the oxide trap charge density of the film was 1.8$\times$10-8C/$\textrm{cm}^2$ and the breakdown field strength was about 10MV/cm.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.27 no.6
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• pp.350-355
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• 2014

Bottom-gate tin oxide ($SnO_2$) thin film transistors (TFTs) were fabricated on $N^+$ Si wafers used as gate electrodes. 60-nm-thick $SnO_2$ thin films acting as active layers were sputtered on $SiO_2/Al_2O_3$ films. The $SiO_2/Al_2O_3$ films deposited on the Si wafers were employed for gate dielectrics. In order to increase the resistivity of the $SnO_2$ thin films, oxygen mixed with argon was introduced into the chamber during the sputtering. The mobility of $SnO_2$ TFTs was measured as a function of the flow ratio of oxygen to argon ($O_2/Ar$). The mobility variation with $O_2/Ar$ was analyzed through studies on crystallinity, oxygen binding state, optical properties. X-ray diffraction (XRD) and XPS (X-ray photoelectron spectroscopy) were carried out to observe the crystallinity and oxygen binding state of $SnO_2$ films. The mobility decreased with increasing $O_2/Ar$. It was found that the decrease of the mobility is mainly due to the decrease in the polarizability of $SnO_2$ films.

• JSTS:Journal of Semiconductor Technology and Science
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• v.3 no.1
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• pp.27-32
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• 2003

Highly reproducible side-wall process for the fabrication of the fine gate length as small as 40nm was developed. This process was utilized to fabricate 40nm InGaAs HEMTs with the 65% strained channel. With the usage of the dual $SiO_2$ and $SiN_x$ dielectric layers and the proper selection of the etching gas, the final gate length (Lg) was insensitive to the process conditions such as the dielectric over-etching time. From the microwave measurement up to 40GHz, extrapolated fT and fmax as high as 371 and 345 GHz were obtained, respectively. We believe that the developed side-wall process would be directly applicable to finer gate fabrication, if the initial line length is lessened below the l00nm range.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.255-255
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• 2010

Recently, nonvolatile memories (NVM) of various types have been researched to improve the electrical performance such as program/erase voltages, speed and retention times. Also, the charge trap memory is a strong candidate to realize the ultra dense 20-nm scale NVM. Furthermore, the high charge efficiency and the thermal stability of SiC nanocrystals NVM with single $SiO_2$ tunnel barrier have been reported. [1-2] In this study, the SiC charge trap NVM was fabricated and electrical properties were characterized. The 100-nm thick Poly-Si layer was deposited to confined source/drain region by using low-pressure chemical vapor deposition (LP-CVD). After etching and lithography process for fabricate the gate region, the $Si_3N_4/SiO_2/Si_3N_4$ (NON) and $SiO_2/Si_3N_4/SiO_2$ (ONO) barrier engineered tunnel layer were deposited by using LP-CVD. The equivalent oxide thickness of NON and ONO tunnel layer are 5.2 nm and 5.6 nm, respectively. By using ultra-high vacuum magnetron sputtering with base pressure 3x10-10 Torr, the 2-nm SiC and 20-nm $SiO_2$ were successively deposited on ONO and NON tunnel layers. Finally, after deposited 200-nm thick Al layer, the source, drain and gate areas were defined by using reactive-ion etching and photolithography. The lengths of squire gate are $2\;{\mu}m$, $5\;{\mu}m$ and $10\;{\mu}m$. The electrical properties of devices were measured by using a HP 4156A precision semiconductor parameter analyzer, E4980A LCR capacitor meter and an Agilent 81104A pulse pattern generator system. The electrical characteristics such as the memory effect, program/erase speeds, operation voltages, and retention time of SiC charge trap memory device with barrier engineered tunnel layer will be discussed.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.36 no.10
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• pp.1049-1054
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• 2012

Continued advancements in organic materials have led to the development of organic devices that are thin, flexible, and lightweight and that can potentially be used as low-cost energy-conversion devices. While these devices have many advantages, the environmentally induced degradation of the active materials and the low-work-function electrodes remain a valid concern. Hence, many vacuum deposition processes have been applied to develop low-permeation barrier coatings. In this work, we present the results pertaining to the developed thin-film encapsulation. Multilayer encapsulation involves the use of $SiO_x$ or $SiN_x$ with parylene. The effective water vapor transmission rates were investigated using a Ca-corrosion test. The integration of the developed barrier layers was demonstrated by encapsulating pentacene/$C_{60}$ solar cells, and the results are presented.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.28 no.6
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• pp.365-370
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• 2015

Zinc tin oxide transparent thin film transistors (ZTO TTFTs) were fabricated on oxidized $n^+$ Si wafers. The thickness of ~30 nm $Al_2O_3$ films were deposited on the oxidized Si wafers by atomic layer deposition, which acted as the gate insulators of ZTO TTFTs. The $Al_2O_3$ films were rapid-annealed at $400^{\circ}C$, $600^{\circ}C$, $800^{\circ}C$, and $1,000^{\circ}C$, respectively. Active layers of ZTO films were deposited on the $Al_2O_3/SiO_2$ coated $n^+$ Si wafers by rf magnetron sputtering. Mobility and threshold voltage were measured as a function of the rapid-annealing temperature. X-ray photoelectron spectroscopy (XPS) were carried out to observe the chemical bindings of $Al_2O_3$ films. The annealing effects of gate-insulator on the properties of TTFTs were analyzed based on the results of XPS.