• 마이크로전자및패키징학회지
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• 제11권2호
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• pp.29-35
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• 2004

65 nm급 게이트 유전체로의 $HfO_2$의 적용을 위해 hydrogen-terminate된 Si 기판과 ECR $N_2$ plasma를 이용하여 SiNx를 형성한 기판 위에 MOCVD를 이용하여 $HfO_2$를 증착하였다. $450^{\circ}C$에서 증착시킨 박막의 경우 낮은 carbon 불순물을 가지며 비정질 matrix에 국부적인 결정화와 가장 적은 계면층이 형성되었으며 이 계면층은 Hf-silicate임을 알 수 있었다. 또한 $900^{\circ}C$, 30초간 $N_2$분위기에서 RTA 결과 $HfO_2/Si$의 single layer capacitor의 경우 계면층의 증가로 인해 EOT가 열처리전(2.6nm)보다 약 1 nm 증가하였다. 그러나 $HfO_2/SiNx/Si$ stack capacitor의 경우 SiNx 계면층은 열처리후에도 일정하게 유지되었으며 $HfO_2$ 박막의 결정화로 열처리전(2.7nm)보다 0.3nm의 EOT 감소를 나타내었으며 열처리후에도 $4.8{\times}10^{-6}A/cm^2$의 매우 우수한 누설전류 특성을 가짐을 알 수 있었다.

• 한국재료학회지
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• 제17권2호
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• pp.115-120
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• 2007

Polycrystalline silicon (poly-Si) thin film transistors (TFTs) might be fabricated on the mica substrate and transferred to a flexible plastic substrate because mica can be easily cleaved into a thin layer. To overcome the adhesion and stress problem between poly-Si film and mica substrate, a buffer layer consisting of $SiO_x/Ta/Ti$ three layers has been developed. The $SiO_x$ layer is for electrical isolation, the Ti layer is for adhesion of $SiO_{x}$ and mica. and Ta is for stress relief between $SiO_x$ and Ti. A TFT was fabricated on the mica substrate by a conventional Si process and was successfully transferred to a plastic substrate.

• 한국해양공학회:학술대회논문집
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• 한국해양공학회 2002년도 춘계학술대회 논문집
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• pp.29-34
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• 2002

[ $Nb/MoSi_2-ZrO_2$ ] laminate composites have been successfully fabricated by alternately stacking $MoSi_2-ZrO_2$ powder layer and Nb sheet, followed by hot pressing in a graphite mould. The fabricating parameters were selected as hot press temperatures. The instrumented Charpy impact test was carried out at the room temperature in order to investigate the relationship between impact properties and fabricating temperatures. The interfacial shear strength between $MoSi_2-ZrO_2$ and Nb, which is associated with the fabricating temperature and the growth of interfacial reaction layer, is also discussed. The plastic deformation of Nb sheet and the interfacial delamination were macroscopically observed. The $Nb/MoSi_2-ZrO_2$ laminate composites had the maximum impact value when fabricated at 1623K, accompanying the increase of fracture displacement and crack propagation energy. The interfacial shear strength of $Nb/MoSi_2-ZrO_2$ laminate composites increased with the growth of interfacial reaction layer, which resulted from the increase of fabricating temperature. there is an appropriate interfacial shear strength for the enhancement of impact value of $Nb/MoSi_2-ZrO_2$ laminate composites. A large increase of interfacial shear strength restrains the plastic deformation of Nb sheet.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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• pp.127-128
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• 2008

The electrical characteristics of VARIOT (variable oxide thickness) with various $HfO_2$ thicknesses on thin $SiO_2$ or $Al_2O_3$ layer were investigated. Especially, the charge trapping characteristics of $HfO_2$ layer were intensively studied. The thin $HfO_2$ layer has small charge trapping characteristics while the thick $HfO_2$ layer has large memory window. Therefore, the $HfO_2$ layer is superior material and can be applied to charge storage as well as tunneling barrier of the non-volatile memory applications.

• 대한화학회지
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• 제56권4호
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• pp.478-483
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• 2012

We successfully synthesized $Fe_3O_4/SiO_2$ nanoparticles with ultrathin silica layer of $1.0{\pm}0.5$ nm that was fine controlled by changing concentration of $Fe_3O_4$. Among various reaction conditions for silica coating, increasing concentration of $Fe_3O_4$ was more effective approach to decrease silica thickness compared to water-to-surfactant ratio control. Moreover, we found that concentration of the 1-octanol is also important factor to produce the homogeneous $Fe_3O_4/SiO_2$ nanoparticles. The present approach could be available to apply on preparation of other core/shell nanoparticles with ultrathin silica layer.

• 한국전자통신학회논문지
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• 제5권1호
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• pp.81-87
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• 2010

본 논문에서는 유기발광다이오드 적용을 위한 보호막 혹은 barrier 적용을 위하여 화학증착방법(CVD)를 이용한 실리콘 산화막을 형성하고, 산화막의 특성에 영향을 미치는 공정조건을 변화시켰다. 이로부터 HDP-CVD를 활용한 $SiO_2$박막 증착을 위한 최적의 공정조건은 $SiH_4:O_2$=30:60[sccm]유량, 소스와 기판과의 거리가 70 [mm], 기판에 Bias를 가하지 않은 조건인 경우 8~10[mtorr] 공정압력에서 매우 안정된 플라즈마 형성이 가능한 최적의 공정조건을 얻었다. 얻어진 공정조건으로 제작된 $SiO_2$산화막의 모콘테스트를 통한 투습율(WVTR)을 조사한 결과 2.2 [$g/m^2$_day]값으로 HDP-CVD로 제작된 $SiO_2$산화막은 유기발광다이오드용 보호막으로의 적용이 어려울 것으로 생각된다.

• 한국전기전자재료학회논문지
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• 제23권1호
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• pp.24-28
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• 2010

We have proposed an Buffer layer to improve the transmittance of ITO. Here, $SiO_2$ and $TiO_2$ were selected as the Buffer layer coating material. The structures of Buffer layer were designed in ITO/$SiO_2/TiO_2$/Glass and ITO/Glass/$TiO_2/SiO_2$. Then, these materials were deposited by ion-assisted deposition system. Transmittances of deposited ITO were 86.14 and 85.07%, respectively. These results show that the proposed structure has higher transmittance than the conventional ITO device.

• 한국표면공학회지
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• 제20권2호
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• pp.49-59
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• 1987

The properties of $Cr_2O_3-Al_2O_3-SiO_2$ composite oxide coatings on steel surface were investigated. The results obtained were as follows: The microhardness of oxide coating layer increased with increasing heat-treatment temperature and $Cr_2O_3$ content in coating layer. The hardness showed the highest value (850Hv) treated at 700$^{\circ}C$ for $SiO_2:Al_2O_3:Cr_2O_3$=1:1:4. Increasing heat-treatment temperature, corrosion current density became lower and coating layer became denser. The corrosion current density showed the lowest value $(6.5{\times}10^{-5}\;Acm^2)$ treated at 750$^{\circ}C\;for\;SiO_2:Al_2O_3:Cr_2O_3$=1:1:3. These results were explained by protective layer which was formed during heat-treatment. The bonding between matrix and coating layer is expected to be made mechanically and chemically by the inter diffusion of Ni and Fe. The composite oxide coating was formed by softening of the binder with increasing heat-treatment temperature. The strengthening of coating layer is to be resulted from the dispersion of major oxide particles.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2004년도 추계학술대회 논문집 전기물성,응용부문
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• pp.183-186
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• 2004

The metal-ferroelectric-insulator-semiconductor(MFIS) capacitors were fabricated using a metalorganic decomposition (MOD)method. The $CeO_2$ thin films were deposited as a buffer layer on Si substrate and $Bi_{3.25}La_{0.75}Ti_3O_{12}$ (BLT) thin films were used as a ferroelectric layer. The electrical and structural properties of the MFIS structure were investigated by varying the $CeO_2$ layer thickness. The width of the memory window in the capacitance-voltage (C-V)curves for the MFIS structure decreased with increasing thickness of the $CeO_2$ layer. Auger electron spectroscopy (AES) and transmission electron microscopy (TEM) show no interdiffusion by using the $CeO_2$ film as buffer layer between the BLT film and Si substrate. The experimental results show that the BLT-based MFIS structure is suitable for non-volatile memory field-effect-transistors (FETs) with large memory window.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2011년도 제40회 동계학술대회 초록집
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• pp.134-134
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• 2011

High-k dielectric materials such as $HfO_2$, $ZrO_2$ and $Al_2O_3$ increase gate capacitance and reduce gate leakage current in MOSFET structures. This behavior suggests that high-k materials will be promise candidates to substitute as a tunnel barrier. Furthermore, stack structure of low-k and high-k tunnel barrier named variable oxide thickness (VARIOT) is more efficient.[1] In this study, we fabricated the $WSi_2$ nanocrystals nonvolatile memory device with $SiO_2/HfO_2/Al_2O_3$ tunnel layer. The $WSi_2$ nano-floating gate capacitors were fabricated on p-type Si (100) wafers. After wafer cleaning, the phosphorus in-situ doped poly-Si layer with a thickness of 100 nm was deposited on isolated active region to confine source and drain. Then, on the gate region defined by using reactive ion etching, the barrier engineered multi-stack tunnel layers of $SiO_2/HfO_2/Al_2O_3$ (2 nm/1 nm/3 nm) were deposited the gate region on Si substrate by using atomic layer deposition. To fabricate $WSi_2$ nanocrystals, the ultrathin $WSi_2$ film with a thickness of 3-4 nm was deposited on the multi-stack tunnel layer by using direct current magnetron sputtering system [2]. Subsequently, the first post annealing process was carried out at $900^{\circ}C$ for 1 min by using rapid thermal annealing system in nitrogen gas ambient. The 15-nm-thick $SiO_2$ control layer was deposited by using ultra-high vacuum magnetron sputtering. For $SiO_2$ layer density, the second post annealing process was carried out at $900^{\circ}C$ for 30 seconds by using rapid thermal annealing system in nitrogen gas ambient. The aluminum gate electrodes of 200-nm thickness were formed by thermal evaporation. The electrical properties of devices were measured by using a HP 4156A precision semiconductor parameter analyzer with HP 41501A pulse generator, an Agillent 81104A 80MHz pulse/pattern generator and an Agillent E5250A low leakage switch mainframe. We will discuss the electrical properties for application next generation non-volatile memory device.