• JSTS:Journal of Semiconductor Technology and Science
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• v.1 no.4
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• pp.202-208
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• 2001

In Recent results suggested that doping $Ta_2O_5$ with a small amount of $TiO_2$ using standard ceramic processing techniques can increase the dielectric constant of $Ta_2O_5$ significantly. In this paper, this concept is studied using RTCVD (Rapid Thermal Chemical Vapor Deposition). Ti-doped $Ta_2O_5$ films are deposited using $TaC_{12}H_{30}O_5N$, $C_8H_{24}N_4Ti$, and $O_2$ on both Si and $NH_3$-nitrided Si substrates. An $NH_3$-based interface layer at the Si surface is used to prevent interfacial oxidation during the CVD process and post deposition annealing is performed in $H_2/O_2$ ambient to improve film quality and reduce leakage current. A sputtered TiN layer is used as a diffusion barrier between the Al gate electrode and the $TaTi_xO_y$ dielectric. XPS analyses confirm the formation of a ($Ta_2O_5)_{1-x}(TiO_2)_x$ composite oxide. A high quality $TaTi_xO_y$ gate stack with EOT (Equivalent Oxide Thickness) of $7{\AA}$ and leakage current $Jg=O.5A/textrm{cm}^2$ @ Vg=-1.0V has been achieved. We have also succeeded in forming a $TaTi_x/O_y$ composite oxide by rapid thermal oxidation of the as-deposited CVD TaTi films. The electrical properties and Jg-EOT characteristics of these composite oxides are remarkably similar to that of RTCVD $Ta_2O_5, suggesting that the dielectric constant of $Ta_2O_5$ is not affected by the addition of $TiO_2$.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.1494-1495
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• 2009

Thin Film Transistor(TFT) having CIS (CuInSe) semiconductor layer was fabricated and characterized. Heavily doped Si was used as a common gate electrode and PECVD Silicon nitride ($SiN_x$) was used as a gate dielectric material for the TFT. Source and drain electrodes were deposited on the $SiN_x$ layer and CIS layer was formed by a direct patterning method between source and drain electrodes. Nanoparticle of CIS material was used as the ink of the direct patterning method.

• Journal of the Microelectronics and Packaging Society
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• v.11 no.2 s.31
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• pp.29-35
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• 2004

Hafnium-oxide gate dielectric films deposited by a metal organic chemical vapor deposition technique on a $N_2-plasma$ treated SiNx and a hydrogen-terminated Si substrate have been investigated. In the case of $HfO_2$ film deposited on a hydrogen-terminated Si substrate, suppressed crystallization with effective carbon impurity reduction was obtained at $450^{\circ}C$. X-ray photoelectron spectroscopy indicated that the interface layer was Hf-silicate rather than phase separated Hf-silicide and silicon oxide structure. Capacitance-voltage measurements show equivalent oxide thickness of about 2.6nm for a 5.0 nm $HfO_2/Si$ single layer capacitor and of about 2.7 nm for a 5.7 nm $HfO_2/SiNx/Si$ stack capacitor. TEM shows that the interface of the stack capacitor is stable up to $900^{\circ}C$ for 30 sec.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.290-294
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• 2001

In this study, ZnO is evaporated to be coated on n-type Si wafer substrate. Refractive coefficient of thin film that is evaporating TiO$_2$ onto ZnO increases linearly as thickness is getting thinner to have high value and high angle and it satisfies theoretical equation I(x)=Io exp (-$\alpha$x) theory that represents the strength of photon energy advancing through ZnO thin film. And dielectric constant of TiO$_2$ thin film evaporated onto ZnO is high and $\varepsilon$$_2$ is smaller than $\varepsilon$$_1$. The specimen TiO$_2$ thin film evaporated onto ZnO has much higher dielectric constant when photon energy is increased.

• Korean Journal of Materials Research
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• v.10 no.3
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• pp.212-217
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• 2000

Dielectric thin films for TFT(thin film transistor)s, such as silicon nitride$(Si_3N_4)$ and silicon oxide$(SiO_2)$, are usually deposited at $200~300^{\circ}C$. In this study, authors have tried to form dielectric films not by deposition but by oxidation with ECR(Electron Cyclotron Resonance) oxygen plasma, to improve the interface properties was not intensionally heated during oxidation. THe oxidation was performed consecutively without breaking vacuum after the deposition of a-Si: H films on the substrate to prevent the introduction of impurities. In this study, especially pulse mode of microwave power has been firstly tried during FCR oxygen plasma formation. Compared with the case of the continuous wave mode, the oxidation with the pulsed ECR results in higher quality silicon oxide$SiO_X$ films in terms of stoichiometry of bonding, dielectric constants and surface roughness. Especially the surface roughness of the pulsed ECR oxide films dramatically decreased to one-third of that of the continuous wave mode cases.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.2
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• pp.117-123
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• 2004

A 30 nm $In_{0.7}GaAs$ High Electron Mobility Transistor (HEMT) with triple-gate has been successfully fabricated using the $SiO_2/SiN_x$ sidewall process and BCB planarization. The sidewall gate process was used to obtain finer lines, and the width of the initial line could be lessened to half by this process. To fill the Schottky metal effectively to a narrow gate line after applying the developed sidewall process, the sputtered tungsten (W) metal was utilized instead of conventional e-beam evaporated metal. To reduce the parasitic capacitance through dielectric layers and the gate metal resistance ($R_g$), the etchedback BCB with a low dielectric constant was used as the supporting layer of a wide gate head, which also offered extremely low Rg of 1.7 Ohm for a total gate width ($W_g$) of 2x100m. The fabricated 30nm $In_{0.7}GaAs$ HEMTs showed $V_{th}$of -0.4V, $G_{m,max}$ of 1.7S/mm, and $f_T$ of 421GHz. These results indicate that InGaAs nano-HEMT with excellent device performance could be successfully fabricated through a reproducible and damage-free sidewall process without the aid of state-of-the-art lithography equipment. We also believe that the developed process will be directly applicable to the fabrication of deep sub-50nm InGaAs HEMTs if the initial line length can be reduced to below 50nm order.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.381-381
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• 2010

$(ZrO_2)_{0.66}(HfO_2)_{0.34}$ thin films as gate dielectrics have been proposed to overcome the problems of tunneling current and degradation mobility inachieving a thin equivalent oxide thickness. An extremely thin $SiO_2$ layer is used in order to separate the carrier in MOSFET channel from the dielectric field fluctuation caused by phonons in the dielectric which decreases the carrier mobility. The electronic and optical properties influenced the device performance to a great extent. $(ZrO_2)_{0.66}(HfO_2)_{0.34}$ dielectric films on p-Si (100) were grown by atomic layer deposition method, for which the conduction band offsets, valence band offsets and band gapswere obtained by using X-ray photoelectron spectroscopy and reflection electron energy loss spectroscopy. The band gap, valence and conduction band offset values for $(ZrO_2)_{0.66}(HfO_2)_{0.34}$ dielectric thin film, grown on Si substrate were about 5.34, 2.35 and 1.87 eV respectively. This band alignment was similar to that of $ZrO_2$. In addition, The dielectric function (k, $\omega$), index of refraction n and the extinction coefficient k for the $(ZrO_2)_{0.66}(HfO_2)_{0.34}$ thin films were obtained from a quantitative analysis of REELS data by comparison to detailed dielectric response model calculations using the QUEELS-$\varepsilon$(k, $\omega$)-REELS software package. These optical properties are similar with $ZrO_2$ dielectric thin films.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.05b
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• pp.106-109
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• 2005

The $(Sr_{1-x}Ca_x)TiO_3$(SCT) thin films are deposited on Pt-coated electrode (Pt/TiN/$SiO_2$/Si) using RF sputtering method with substitutional contents of Ca. The optimum conditions of RF power and Ar/$O_2$ ratio were 140[W] and 80/20, respectively. Deposition rate of SCT thin film was about 18.75[$\AA$/min]. The dielectric constant was increased with increasing the substitutional contents of Ca, while it was decreased if the substitutional contents of Ca exceeded over 15[mol%]. The capacitance characteristics had a stable value within ${\pm}4$[%] in temperature ranges of -80~+90[$^{\circ}C$].

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.51 no.8
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• pp.340-346
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• 2002

Capacitor material utilized in the downsizing passive devices and integration of passive devices requires the physical and electrical properties at given area such as capacitor thickness reduction, relative dielectric constant increase, low leakage current and thermal stability. common capacitor materials, $Al_2O_3$, $SiO_2$, $Si_3N_4$, $SiO_2$/$Si_3N_4$, TaN and et al., used until recently have reached their physical limits in their application to integration of passive devices. $Ta_2O_{5}$ is known to be a good alternative to the existing materials for the capacitor application because of its high dielectric constant (25~35), low leakage current and high breakdown strength. Despite the numerous investigations of $Ta_2O_{5}$ material, there have little been established the clear understanding of the annealing effect on capacitance characteristic and conduction mechanism. This study presents the dielectric properties $Ta_2O_{5}$ MIM capacitor structure Processed by $O_2$ RTA oxidation. X-ray diffraction patterns showed the existence of amorphous phase in $600^{\circ}C$ annealing under the $O_2$ RTA and the formation of preferentially oriented-$Ta_2O_{5}$ in 650, $700^{\circ}C$ annealing and the AES depth profile showed $O_2$ RTA oxidation effect gives rise to the $O_2$ deficientd into the new layer. The leakage current density respectively, at 3~1l$\times$$10_{-2}$(kV/cm) were $10_{-3}$~$10_{-6}$(A/$\textrm{cm}^2$). In addition, behavior is stable irrespective of applied electric field. the frequency vs capacitance characteristic enhanced stability more then $Ta_2O_{5}$ thin films obtained by $O_2$ reactive sputtering. The capacitance vs voltage measurement that, Vfb(flat-band voltage) was increase dependance on the $O_2$ RTA oxidation temperature.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07a
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• pp.177-180
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• 2002

Thickness dependence of crystallographic orientation of diol based sol-gel derived PZT(52/48) films on dielectric and piezoelectric properties was investigated The thickness of each layer by one time spinning was about 0.2 $\mu\textrm{m}$, and crack-free films was successfully deposited on 4 inches Pt/Ti/SiO$_2$/Si substrates by 0.5 mol solutions in the range from 0.2 $\mu\textrm{m}$ to 3.8 $\mu\textrm{m}$. Excellent P-E hysteresis curves were achieved without pores or any defects between interlayers. As the thickness increased , the (111) preferred orientation disappeared from 1$\mu\textrm{m}$ to 3 $\mu\textrm{m}$ region, and the orientation of films became random above 3 $\mu\textrm{m}$. Dielectric constants and longitudinal piezoelectric coefficient d$\_$33/, measured by pneumatic method were saturated around the value of about 1400 and 300 pC/N respectively above the thickness of 0.8 7m. A micromachined piezoelectric cantilever have been fabricated using 0.8 $\mu\textrm{m}$ thickness PZT (52/48) films. PZT films were prepared on Si/SiN$\_$x/SiO$_2$/Ta/Pt substrate and fabricated unimorph cantilever consist of a 0.8 fm thick PZT layer on a SiNx elastic supporting layer, which becomes vibration when ac voltage is applied to the piezoelectric layer. The dielectric constant (at 100 kHz) and remanent polarization of PZT films were 1050 and 25 ${\mu}$C/$\textrm{cm}^2$, respectively. Electromechanical characteristics of the micromachined PZT cantilever in air with 200-600 $\mu\textrm{m}$ lengths are discussed in this presentation.