• E2M - 전기 전자와 첨단 소재
• /
• 제9권1호
• /
• pp.30-37
• /
• 1996

Previously, crystallization of a-Si:H films on glass substrates were limited to anneal temperature below 600.deg. C, over 10 hours to avoid glass shrinkage. Our study indicates that the crystallization is strongly influenced by anneal temperature and weakly affected by anneal duration time. Because of the high temperature process and nonconducting substrate requirements for poly-Si TFTs, the employed substrates were limited to quartz, sapphire, and oxidized Si wafer. We report on poly-Si TFT's using high temperature anneal on a Si:H/Mo structures. The metal Mo substrate was stable enough to allow 1000.deg. C anneal. A novel TFT fabrication was achieved by using part of the Mo substrate as drain and source ohmic contact electrode. The as-grown a-Si:H TFT was compared to anneal treated poly-Si TFT'S. Defect induced trap states of TFT's were examined using the thermally stimulated current (TSC) method. In some case, the poly-Si grain boundaries were passivated by hydrogen. A-SI:H and poly-Si TFT characteristics were investigated using an inverted staggered type TFT. The poly -Si films were achieved by various anneal techniques; isothermal, RTA, and excimer laser anneal. The TFT on as grown a-Si:H exhibited a low field effect mobility, transconductance, and high gate threshold voltage. Some films were annealed at temperatures from 200 to >$1000^{\circ}C$ The TFT on poly-Si showed an improved $I_on$$I_off$ ratio of $10_6$, reduced gate threshold voltage, and increased field effect mobility by three orders. Inverter operation was examined to verify logic circuit application using the poly Si TFTs.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2002년도 하계종합학술대회 논문집(2)
• /
• pp.245-248
• /
• 2002

In this paper, the influence of Si surface damage on the NiSi formation has been characterized. The silicon surface is damaged using ion beam type spotter. Then, the effect of H2 anneal and TiN capping layer on the damaged has also been analyzed. The sheet resistance of NiSi formed on damaged Si increased rapidly as the damaging time increases while thermal stability of damaged NiSi was stabler than the undamaged one. In the case when H\ulcorner anneal and TiN capping layer were applied together, the characteristics of NiSi shows a little improvement of the sheet resistance.

• Journal of Magnetics
• /
• 제6권4호
• /
• pp.126-128
• /
• 2001

The effect of rapid thermal anneal (RTA) has been investigated on the properties of an FeMn exchange-biased magnetic tunnel junction (MTJ) using magnetoresistance and I-V measurements and transmission electron microscopy (TEM). The tunneling magnetoresistance (TMR) in an as-grown MTJ is found to be ∼27%, while the TMR in MTJs annealed by RTA increases with annealing temperature up to 300$\^{C}$, reaching ∼46%. A TEM image reveals a structural change in the interface of A1$_2$O$_3$layer for the MTJ annealed by RTA at 300$\^{C}$. The oxide barrier parameters are found to vary abruptly with annealing time within a few ten seconds. Our results demonstrate that the present RTA enhances the magnetoresistive properties of MTJs.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2002년도 추계학술대회 논문집 Vol.15
• /
• pp.167-170
• /
• 2002

The influence of Si surface damage on Ni-silicide with TiN Capping layer and the effect of $H_2$ anneal are characterized. Si surface is intentionally damaged using Ar Sputtering. The sheet resistance of NiSi formed on damaged silicon increased rapidly as Ar sputtering time increased. However, the thermal stability of Ni-Si on the damage silicon was more stable than that on at undamaged Si, which means that damaged region retards the formation of NiSi. It was shown that $H_2$ anneal and TiN capping is highly effective in reducing NiSi sheet resistance.

• Transactions on Electrical and Electronic Materials
• /
• 제1권2호
• /
• pp.7-11
• /
• 2000

a-Si:H and poly-Si TFT(thin film transistor) characteristics were investigated using an inverted staggered type TFT. The TFT an as-grown a-Si:H exhibited a low field effect mobility, transconductance, and high gate threshold voltage. The poly-Si films were achieved by using an isothermal and RTA treatment for glow discharge deposited a-Si:H films. The a-Si:H films were cystallized at the various temperature from 600$^{\circ}C$ to 1000$^{\circ}C$. As anneal temperature was elevated, the TFT exhibited increased g$\sub$m/ and reduced V$\sub$ds/. V$\sub$T/. The poly-Si grain boundary passivation with grain boundary trap types and activation energies as a function of anneal temperature. The poly-si TFT showed an improved I$\sub$nm//I$\sub$off/ ratio of 10$\^$6/, reduced gate threshold voltage, and increased field effect mobility by three orders.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제1권2호
• /
• pp.95-102
• /
• 2001

Hafnium oxide thin films for gate dielectric were deposited at $300^{\circ}C$ on p-type Si (100) substrates by plasma enhanced chemical vapor deposition (PECVD) and annealed in $O_2$ and $N_2$ ambient at various temperatures. The effect of hydrogen treatment in 4% $H_2$ at $350^{\circ}C$ for 30 min on the electrical properties of $HfO_2$for gate dielectric was investigated. The flat-band voltage shifts of $HfO_2$capacitors annealed in $O_2$ambient are larger than those in $N_2$ambient because samples annealed in high oxygen partial pressure produces the effective negative charges in films. The oxygen loss in $HfO_2$films was expected in forming gas annealed samples and decreased the excessive oxygen contents in films as-deposited and annealed in $O_2$ or $N_2$ambient. The CET of films after hydrogen forming gas anneal almost did not vary compared with that before hydrogen gas anneal. Hysteresis of $HfO_2$films abruptly decreased by hydrogen forming gas anneal because hysteresis in C-V characteristics depends on the bulk effect rather than $HfO_2$/Si interface. The lower trap densities of films annealed in $O_2$ambient than those in $N_2$were due to the composition of interfacial layer becoming closer to $SiO_2$with increasing oxygen partial pressure. Hydrogen forming gas anneal at $350^{\circ}C$ for samples annealed at various temperatures in $O_2$and $N_2$ambient plays critical role in decreasing interface trap densities at the Si/$SiO_2$ interface. However, effect of forming gas anneal was almost disappeared for samples annealed at high temperature (about $800^{\circ}C$) in $O_2$ or $N_2$ambient.

• 센서학회지
• /
• 제6권6호
• /
• pp.483-490
• /
• 1997

Thin film Si has been used in sensors, radiation detectors, and solar cells. The carrier mobility of thin film Si influences the device behavior through its frequency response or time response. Since poly-Si shows the higher mobility value, a-Si:H films on Mo substrate were subjected to various crystallization treatments. Consequently, we need to find an appropriate method in mobility measurement before and after the anneal treatment. This paper investigates the carrier mobility improvement with anneal treatments and summarizes the mobility measurement methods of the a-Si:H and poly-Si film. Various techniques were investigated for the mobility determination such as Hall mobility, HS, TOF, SCLC, TFT, and TCO method. We learned that TFT and TCO method are suitable for the mobility determination of a-Si:H and poly-Si film. The measured mobility was improved by $2{\sim}3$ orders after high temperature anneal above $700^{\circ}C$ and grain boundary passivation using an RF plasma rehydrogenation.

• 한국전기전자재료학회논문지
• /
• 제22권12호
• /
• pp.1095-1099
• /
• 2009

As a substitute material for silicon, we synthesized few layer graphene (FLG) by CVD process with a 300-nm-thick nickel film deposited on the silicon substrate and found out the lowest temperature for graphene synthesis. Raman spectroscopy study showed that the D peak (wave length : ${\sim}1,350\;cm^{-1}$) of graphene was minimized and then the 2D one (wave length : ${sim}2,700\;cm^{-1}$) appeared when rapid thermal anneal is carried out with the $C_2H_2$ treated nickel film. This study demonstrates that a high quality FLG formed at a low temperature of $400^{\circ}C$ is applicable as CMOS devices and transparent electrode materials.

• 한국진공학회지
• /
• 제17권3호
• /
• pp.199-203
• /
• 2008

$O_2$ 플라즈마를 이용한 표면처리 공정이 Bio-FET (biologically sensitive field-effect transistor)에 미치는 영향을 조사하기 위하여, SOI (Silicon-on-Insulator) wafer와 sSOI (strained- Si-on-Insulator) wafer를 이용하여 pseudo-MOSFET을 제작하고 $O_2$ 플라즈마를 이용하여 표면처리를 진행하였다. 제작된 시료들은 back gated metal contact junction 방식으로 측정되었다. $I_D-V_G$ 특성과 field effect mobility 특성의 관찰을 통하여 $O_2$ 플라즈마 표면처리에 따른 각 시료들의 전기적 특성 변화에 대하여 관찰하였다. 그리고 $O_2$ 플라즈마 표면처리 과정에서 플라즈마에 의한 손상을 받은 시료들은 2% 수소희석가스 ($H_2/N_2$)를 이용한 후속 열처리 공정을 진행한 후 전기적 특성이 향상되는 것을 관찰할 수 있었다. 이는 수소희석가스를 이용한 후속 열처리 공정을 통하여 산화막과 Si 사이의 계면 준위와 산화막 내부의 전하 포획 준위를 감소시켰기 때문이다.

• 한국전기전자재료학회논문지
• /
• 제16권4호
• /
• pp.280-285
• /
• 2003

The influence of silicon surface damage on nickel-silicide (NiSi) has been characterized and H$_2$ anneal and TiN rapping has been applied to suppress the electrical, morphological deterioration phenomenon incurred by the surface damage. The substrate surface is intentionally damaged using Ar IBE (Ion beam etching) which can Precisely control the etch depth. The sheet resistance of NiSi increased about 18% by the surface damage, which is proven to be mainly due to the reduced silicide thickness. It is shown that simultaneous application of H: anneal and TiN capping layer is highly effective in suppressing the surface damage effect.