In ahigh power amplifier design, power combiner/divider is used to connect low power amplifiers in parallel. The raidal structure of the powe combiner/divider has not only a good characteristics of port-to-port isolation but also an advantage of giving a redundancy to the structure itself by using RF switches. The parastics of a power resistor, that would be a problem in design process, are removed by both slot lines and cavity resonators, and the comon node in the circuit is rdesigned as a planar topology, and thus a new type of 4-way radial power combiner/divider is accomplished at 1840 ~ 1870 MH PCS frequency band. The insertion loss, reflection, and isolation characteristics of 40way radial power combiner/divider which can be adaptable to PCS system in this thesis are -0.3dB, -24dB,a dn -27dB respectively.

RuO$_{2}$ thin films are prepared by RF magnetron reactive sputtering and their characteristics of crystallization, microstructue, surface roughness and resistivity are studied with various O$_{2}$/(Ar+O$_{2}$) ratios and substrate temperatures. As O$_{2}$/(Ar+O$_{2}$) ratio decreas and substrate temperature increases, the preferred growing plane of RuO$_{2}$ thin films are changed from (110) to (101) plane. With increase of the O$_{2}$/(Ar+O$_{2}$) ratio from 20% to 50%, the surface roughness and the resistivity of RuO$_{2}$ thin films increase form 2.38nm to 7.81 nm, and from 103.6.mu..ohm.-cm to 227.mu..ohm.-cm, resepctively, but the deposition rate decreases from 47 nm/min to 17nm/min. On the other hand, as the substrate temperature increases form room temperature to 500.deg. C, resistivity decreases from 210.5.mu..ohm.-cm to 93.7.mu..ohm.-cm. RuO$_{2}$ thin film deposited at 300.deg. C shows a execellent surface roughness of 2.38nm. As the annealing temperature increases in the range between 400.deg. C and 650.deg. C, the resistivity decreases because of th improvement of crystallinity. We find that RuO$_{2}$ thin film deposited at 20% of O$_{2}$/(Ar+O$_{2}$) ratio and 300.deg. C of substrate temperature shows execellent combination of surface smoothness and low resistrivity so that it is well qualified for bottom electrodes for ferroelectric thin films.

The integration method of carier concentrations to redcue the discretization error of th box integratio method used in the discretization of the three-dimensional poisson's equation is presented. The carrier concentration is approximated in the closed form as an exponential function of the linearly varying potential in the element. The presented method is implemented in the three-dimensional poisson's equation solver running under the windows 95. The accuracy and the convergence chaacteristics of the three-dimensional poisson's equation solver are compared with those of DAVINCI for the PN junction diode and the n-MOSFET under the thermal equilibrium and the DC reverse bias. The potential distributions of the simulatied devices from the three-dimensional poisson's equation solver, compared with those of DAVINCI, has a relative error within 2.8%. The average number of iterations needed to obtain the solution of the PN junction diode and the n-MOSFET using the presented method are 11.47 and 11.16 while the those of DAVINCI are 21.73 and 23.0 respectively.

To develop ultrathin gate oxide for ULSI MOSFETs, for the first time, we fabricated MOS capacitors with 65.angs. thick initial oxide grown by high pressure oxidation (HIPOX) at 700.deg. C in 5 atmosphere $O_{2}$ ambient and then followed by rapid thermal nitridation (RTN) in N$_{2}$O ambient. The dielectric breakdown fields of the initial HIPOX oxide are 13.0 MV/cm and 13.8MV/cm for negative and positive gate bias, respectively and are dependent on nitridation temeprature and time.The lifetimes of the HIPOX oxides extractd by TDDB method are 1.1*10$^{8}$ sec and 3.4 * 10$^{9}$ sec for negative and positive stress current, respectively. The lifetime of the HIPOX oxide dfor negative stress current increases with nitridation time in N$_{2}$O ambient at 1100.deg.C, reaching maximum value stress curretn increases with nitridation time in N$_{2}$O ambient at 1100.deg. C reacing maximum value of 1.2*10$^{9}$ sec for 30 sec of nitridation time, and then subsequently decreases at the longer nitridation time. The lifetimes of the nitrided-HIPOX oxides are longer than 10 years when nitridations are carried out longer than about 50 sec and 12 sec at 1000.deg. C, and 1100.deg. C, respectively.

To suppress the short channel effects in nMOSFET with 0.1.mu.m channel length, we have fabricated and characterized the ISRC n MOSFET with several process condition. When the recess oxide thickness is 100nm and the channel dose for threshold voltge adjustment is 6*10$^{12}$ /c $m^{-2}$ , B $F_{2}$$^{+}$, the maximum transconductance at $V_{DS}$ =2.0V is 455mS/mm and the BIDL is kept within 67mV. By comparing the ISRC n MOSFET with the conventioanl SHDD (shallowly heavily dopped drain) nMOSFET, we verify the suppression of short channel effects ISRC structure.e.

The device simulator (BANDIS) which can analyze efficiently the electrical characteristics of the semiconductor devices under the three dimensional stationary conditions on the IBM PC was developed. Poisson, electon and hole continuity equations are discretized y te galerkin method using a tetrahedron as af finite element. The frontal solver which has exquisite data structures and advanced input/output functions is dused for the matrix solver which needs the highest cost in the three dimensional device simulation. The discretization method of the continuity equations used in BANDIS are compared with that of the scharfetter-gummel method used in the commercial three-dimensional device. To verify an accuracy and the efficiency of the discretization method, the simulation results of the PN junction diode and the BJT from BANDIS are compared with those of the commercial three-dimensiional device simulator such as DAVINCI. The maximum relative error within 2% and the average number of iterations needed for the convergence is decreased by more than 20%. The total simulation time of the BJT with 25542 nodes is decreased to about 60% compared with that of DAVINCI.

In this paper it is proposed a new architecture for N*N optical packet switching system. It consists of active-splitter type pf packet router, travelling type of optical buffer memory for packet contention resoltuion and an electronic controller. the BER performance of the proposed switching system is analyzed with respect to channel crosstalks and amplified spontaneous emissio noise form switching elements and optical amplifiers respectively. Operational validity of the proposed switching system is also experimentally proved by realizing 2*2 optical packet switching system.

In this paper, we presetn a new method to display 3-D image modelled as a sum of 2-D sliced images by expanding the concept of the conventional 2-D optical correlator based on spatial matched filtr to the 3-D region. It is hsown that a arbitrary image can be constructed by an array of the correlation-peaks between pixel-to-pixel and propose the systhesis precedure of 3-D spatial-matched-fjilter using fresnel diffraction equation to display 3-D image in space. It is also shown that the quantization problem is severe when the systehsised filter function is displayed on the conventional LC-SLM. To overcome this problem, anonlinear quantizaton method using the sigmoid function is suggested, and this method can reduce the bias and the loss of high spatial-frequency information, and improve the diffraction efficiency. Finally, the suggested method is tested by computer simulation and then approved by some optical experiments with the conventional LC-SLM.

Bulged-type bends with low bending loss are newly proposed, and the FD-BPM is made use of for designing optimum structure. How to evaluate bending loss of conventional bends and how to improve the bending structure based on the phase compensation concept are described in genral. Besides simulation results for the bulged-type bends, results for the coupled-type bends and the chamfered-type bends show the most superior performance in terms of not only the bending loss but also the design tolerance.

H:LiNbO$_{3}$ optical modulator buffered by parylene layer, which has a merits in the bandwidth, power consumption and fabrication as compared with conventional SiO$_{2}$ buffered optical modulator, is proposed and analyzed. The dependences of velocity matching condition, charcteristics impedance, and driving voltage on dielectric constants, thickness of buffer layer, and electrode configurations are demonstrated with finite element calculation. And we performed the physical and chemical test of parylene buffer layer deposited on LiNbO$_{3}$ and under Au electrodes.