• Journal of the Korean Solar Energy Society
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• v.33 no.2
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• pp.11-17
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• 2013

Silicon nitride($SiN_x:H$) deposited by radio frequency plasma enhanced chemical vapor deposition(RF-PECVD) is commonly used for anti-reflection coating and passivation in crystalline silicon solar cell fabrication. In this paper, characteristics of the deposited silicon nitride was studied with change of working pressure, deposition temperature, gas ratio of $NH_3$ and $SiH_4$, and RF power during deposition. The deposition rate, refractive index and effective lifetime were analyzed. The (100) p-type silicon wafers with one-side polished, $660-690{\mu}m$, and resistivity $1-10{\Omega}{\cdot}cm$ were used. As a result, when the working pressure increased, the deposition rate of SiNx was increased while the effective life time for the $SiN_x$-deposited wafer was decreased. The result regarding deposition temperature, gas ratio and RF power changes would be explained in detail below. In this paper, the optimized condition in silicon nitride deposition for silicon solar cell was obtained as 1.0 Torr for the working pressure, $400^{\circ}C$ for deposition temperature, 500 W for RF power and 0.88 for $NH_3/SiH_4$ gas ratio. The silicon nitride layer deposited in this condition showed the effective life time of > $1400{\mu}s$ and the surface recombination rate of 25 cm/s. The crystalline silicon solar cell fabricated with this SiNx coating showed 18.1% conversion efficiency.

• Bulletin of the Korean Chemical Society
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• v.35 no.1
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• pp.35-38
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• 2014

Herein, we report on the preparation of red fluorescent Si nanoparticles stabilized with styrene. Nano-sized Si particles emit fluorescence under UV excitation, which could be used to open up new applications in the fields of optics and semi-conductor research. Unfortunately, conventional methods for the preparation of red fluorescent Si nanoparticles suffer from the lack of a fully-established standard synthesis protocol. A common initial approach during the preparation of semi-conductors is the etching of crystalline Si wafers in a HF/ethanol/$H_2O$ bath, which provides a uniformly-etched surface of nanopores amenable for further nano-sized modifications via tuning of various parameters. Subsequent sonication of the etched surface crumbles the pores on the wafer, resulting in the dispersion of particles into the solution. In this study, we use styrene to occupy these platforms to stabilize the surface. We determine that the liberated silicon particles in ethanol solution interact with styrene, resulting in the substitution of Si-H bonds with those of Si-C as determined via UV photo-catalysis. The synthesized styrene-coated Si nanoparticles exhibit a stable, bright, red fluorescence under excitation with a 365 nm UV light, and yield approximately 100 mg per wafer with a synthesis time of 2 h. We believe this protocol could be further expanded as a cost-effective and high-throughput standard method in the preparation of red fluorescent Si nanoparticles.

• Clean Technology
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• v.17 no.4
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• pp.300-305
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• 2011

A mixture of supercritical carbon dioxide and a co-solvent was employed to strip a high-dose ion-implanted photoresist (HDIPR) from the surface of semiconductor wafers. The stripping efficiency was highly improved by the physical force generated from a ultrasonication tip inside the reactor. In addition, helium gas was injected in the reactor as a barrier gas before the introduction of pure supercritical $CO_2$ ($scCO_2$), which reduced the rinsing time significantly. The effect of co-solvents on the stripping efficiency was investigated. The wafer surfaces were analyzed by scanning electron microscopy and by an energy dispersive X-ray spectrometer.

• Clean Technology
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• v.24 no.3
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• pp.157-165
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• 2018

In this study, the removal of $Si_3N_4$ particles from the surface of a silicon wafer was investigated by using supercritical carbon dioxide, the IPA co-solvent and cleaning additive chemicals. First, the solubility of several surfactants and binders in supercritical carbon dioxide solubility and particle dispersibility in the binders were evaluated in order to confirm their suitability for the supercritical cleaning process. Particle removal experiments were carried out with adjusting various process parameters and reaction conditions. The surfactants used in the experiment showed little particle removal effect, producing secondary contamination on the surface of wafers. On the other hand, 5 wt% (with respect to $scCO_2$) of the cleaning additive mixture of trimethyl phosphate, IPA, and trace HF resulted in 85% of particle removal efficiency after $scCO_2$ flowing for 4 minutes at $50^{\circ}C$, 2000 psi, and the flow rate of $15mL\;min^{-1}$.

• Journal of Digital Contents Society
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• v.5 no.4
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• pp.251-256
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• 2004

The flatness of a silicon wafer concerned with ULSI chip is one of the most critical parameters ensuring high yield of wafers. That is necessary to constitute the circuit with high quality for he surface of silicon wafer, which comes to be base to make the direct circuit of the semiconductor, Flatness, therefore, is the most important factor to guarantee it wafer with high quality. The process of polishing is one of the most crucial production line among 10 processing stages to change the rough surface into the flatnees with best quality. Currently at this process, it is general for an engineer in charge to observe, judge and control the model of wafer from the monitor of measuring equipment with his/her own eyes to enhance the degree of flatness. This, however, is quite a troublesome job for someone has to check of process by one's physical experience. The purpose of this study is to approach the model of wafer with digital contents and to apply the result of the research for an algorithm which enables to control the polishing process by means of measuring the degree of flatness automatically, not by person, but by system. In addition, this paper shows that this algorithm proposed for the whole wafer flatness enables to draw an estimated algorithm which is for the thickness of sites to measure the degree of flatness for each site of wafer.

• Journal of the Korean Chemical Society
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• v.47 no.6
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• pp.608-613
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• 2003

In order to remove particles on surface of post-oxide CMP wafer, new cleaning solution was prepared by mixing with DHF (Diluted HF), nonionic surfactant PAAE (Polyoxyethylene Alkyl Aryl Ether), DMSO (Dimethylsulfoxide) and D.I.W.. Silicone wafers were intentionally contaminated by silica, alumina and PSL (polystylene latex) which had different zeta potentials in cleaning solution. This cleaning solution under megasonic irradiation could remove particles and metals simultaneously at room temperature in contrast to traditional AMP (mixture of $NH_4OH,\;H_2O_2$ and D.I.W) without any side effects such as increasing of microroughness, metal line corrosion and deposition of organic contaminants. This suggests that this cleaning solution would be useful future application with copper CMP in brush cleaning process as well as traditional post CMP cleaning process.

• Journal of the Optical Society of Korea
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• v.18 no.5
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• pp.569-573
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• 2014

We demonstrate a low-cost, superbly efficient way of etching for the nano-, and micro-sized pyramid patterns on (100)-oriented Si wafer surfaces for use as a patterned master. We show a way of producing functional optical films for the viewing angle direction brightness-enhancement of Lambertian LED (light emitting diode)/OLED (organic light emitting diode) planar lighting applications. An optimally formulated KOH (Potassium hydroxide) wet etching process enabled random-positioned, and random size-distributed (within a certain size range) pyramid patterns to be developed over the entire (100) silicon wafer substrates up to 8" and a simple replication process of master patterns onto the PC (poly-carbonate) and PMMA (poly-methyl methacrylate) films were performed. Haze ratio values were measured for several film samples exhibiting excellent values over 90% suitable for LED/OLED lighting purposes. Brightness was also improved by 13~14% toward the viewing angle direction. Computational simulations using LightTools$^{TM}$ were also carried out and turned out to be in strong agreement with experimental data. Finally, we could check the feasibility of fabricating low-cost, large area, high performance optical films for commercialization.

• Korean Journal of Materials Research
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• v.17 no.2
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• pp.73-80
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• 2007

For the sub-65 nm CMOS process, it is necessary to develop a new silicide material and an accompanying process that allows the silicide to maintain a low sheet resistance and to have an enhanced thermal stability, thus providing for a wider process window. In this study, we have evaluated the property and unit process compatibility of newly proposed composite silicides. We fabricated composite silicide layers on single crystal silicon from $10nm-Ni_{1-x}Co_x/single-crystalline-Si(100),\;10nm-Ni_{1-x}Co_x/poly-crystalline-\;Si(100)$ wafers (x=0.2, 0.5, and 0.8) with the purpose of mimicking the silicides on source and drain actives and gates. Both the film structures were prepared by thermal evaporation and silicidized by rapid thermal annealing (RTA) from $700^{\circ}C\;to\;1100^{\circ}C$ for 40 seconds. The sheet resistance, cross-sectional microstructure, surface composition, were investigated using a four-point probe, a field emission scanning probe microscope, a field ion beam, an X-ray diffractometer, and an Auger electron depth profi1ing spectroscopy, respectively. Finally, our newly proposed composite silicides had a stable resistance up to $1100^{\circ}C$ and maintained it below $20{\Omega}/Sg$., while the conventional NiSi was limited to $700^{\circ}C$. All our results imply that the composite silicide made from NiCo alloy films may be a possible candidate for 65 nm-CMOS devices.

• Korean Journal of Materials Research
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• v.17 no.9
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• pp.484-488
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• 2007

Mo(Ti) alloy and pure Cu thin films were subsequently deposited on $SiO_2-coated$ Si wafers, resulting in $Cu/Mo(Ti)/SiO_2$ structures. The multi-structures have been annealed in vacuum at $100-600^{\circ}C$ for 30 min to investigate the outdiffusion of Ti to Cu surface. Annealing at high temperature allowed the outdiffusion of Ti from the Mo(Ti) alloy underlayer to the Cu surface and then forming $TiO_2$ on the surface, which protected the Cu surface against $SiH_4＋NH_3$ plasma during the deposition of $Si_3N_4$ on Cu. The formation of $TiO_2$ layer on the Cu surface was a strong function of annealing temperature and Ti concentration in Mo(Ti) underlayer. Significant outdiffusion of Ti started to occur at $400^{\circ}C$ when the Ti concentration in Mo(Ti) alloy was higher than 60 at.%. This resulted in the formation of $TiO_2/Cu/Mo(Ti)\;alloy/SiO_2$ structures. We have employed the as-deposited Cu/Mo(Ti) alloy and the $500^{\circ}C-annealed$ Cu/Mo(Ti) alloy as gate electrodes to fabricate TFT devices, and then measured the electrical characteristics. The $500^{\circ}C$ annealed Cu/Mo($Ti{\geq}60at.%$) gate electrode TFT showed the excellent electrical characteristics ($mobility\;=\;0.488\;-\;0.505\;cm^2/Vs$, on/off $ratio\;=\;2{\times}10^5-1.85{\times}10^6$, subthreshold = 0.733.1.13 V/decade), indicating that the use of Ti-rich($Ti{\geq}60at.%$) alloy underlayer effectively passivated the Cu surface as a result of the formation of $TiO_2$ on the Cu grain boundaries.

• 한국태양에너지학회:학술대회논문집
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• 2011.11a
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• pp.34-39
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• 2011

Screen printing method is a common way to fabricate the crystalline silicon solar cell with low-cost and high-efficiency. The screen printing metallization use silver paste and aluminum paste for front and rear contact, respectively. Especially the rear contact between aluminum and silicon is important to form the back surface filed (Al-BSF) after firing process. BSF plays an important role to reduces the surface recombination due to $p^+$ doping of back surface. However, Al electrode on back surface leads to bow occurring by differences in coefficient of thermal expansion of the aluminum and silicon. In this paper, we studied the properties of mono crystalline silicon solar cell for rear electrode with aluminum and aluminum-boron in order to characterize bow and BSF of each paste. The 156*156 $m^2$ p-type silicon wafers with $200{\mu}m$ thickness and 0.5-3 ${\Omega}\;cm$ resistivity were used after texturing, diffusion, and antireflection coating. The characteristics of solar cells was obtained by measuring vernier callipers, scanning electron microscope and light current-voltage. Solar cells with aluminum paste on the back surface were achieved with $V_{OC}$ = 0.618V, JSC = 35.49$mA/cm^2$, FF(Fill factor) = 78%, Efficiency = 17.13%.