• New & Renewable Energy
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• v.4 no.2
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• pp.68-73
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• 2008

It is very important that constitution of good hetero-junction interface with a high quality amorphous silicon thin films on very cleaned c-Si wafer for making high efficiency hetero-junction solar cells. For achieving the high efficiency solar cells, the inspection and management of c-Si wafer surface conditions are essential subjects. In this experiment, we analyzed the c-Si wafer surface very sensitively using Spectroscopic Ellipsometer for < ${\varepsilon}2$ > and u-PCD for effective carrier life time, so we accomplished < ${\varepsilon}2$ > value 43.02 at 4.25eV by optimizing the cleaning process which is representative of c-Si wafer surface conditions very well. We carried out that the deposition of high quality hydrogenated silicon amorphous thin films by RF-PECVD systems having high density and low crystallinity which are results of effective medium approximation modeling and fitting using spectroscopic ellipsometer. We reached the cell efficiency 12.67% and 14.30% on flat and textured CZ c-Si wafer each under AM1.5G irradiation, adopting the optimized cleaning and deposition conditions that we made. As a result, we confirmed that spectroscopic ellipsometry is very useful analyzing methode for hetero-junction solar cells which need to very thin and high quality multi layer structure.

• Journal of the Korean Vacuum Society
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• v.14 no.2
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• pp.91-96
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• 2005

The silicon-on-insulator (SOI) wafer fabrication technique has been developed by using ion-cut process, based on proton implantation and wafer bonding techniques. It has been shown by SRIM simulation that 65keV proton implantation is required for a SOI wafer (200nm SOI, 400nm BOX) fabrication. In order to investigate the optimum proton dose and primary annealing condition for wafer splitting, the surface morphologic change has been observed such as blistering and flaking. As a result, effective dose is found to be in the $6\~9\times10^{16}\;H^+/cm^2$ range, and the annealing at $550^{\circ}C$ for 30 minutes is expected to be optimum for wafer splitting. Direct wafer bonding is performed by joining two wafers together after creating hydrophilic surfaces by a modified RCA cleaning, and IR inspection is followed to ensure a void free bonding. The wafer splitting was accomplished by annealing at the predetermined optimum condition, and high temperature annealing was then performed at $1,100^{\circ}C$ for 60 minutes to stabilize the bonding interface. TEM observation revealed no detectable defect at the SOI structure, and the interface trap charge density at the upper interface of the BOX was measured to be low enough to keep 'thermal' quality.

• Journal of Institute of Control, Robotics and Systems
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• v.21 no.12
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• pp.1115-1121
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• 2015

Fast inspection of solder ball bumps in ball grid array (BGA) is an important issue in the flip chip bonding technology. Particularly, semiconductor industry has required faster and more accurate inspection of micron-size solder bumps in flip chip bonding, as the density of balls increase dramatically. In this paper, we describe an inspection approach of BGA balls by using 5-step ring illumination device and normalized cross-correlation (NCC) method. The images of BGA ball by the illumination device show unique and distinguishable characteristic contours by their 3-D shapes, which are called as "iso-slope contours". Template images of reference ball samples can be produced artificially by the hybrid reflectance model and 3D data of balls. NCC values between test and template samples are very robust and reliable under well-structured condition. The 200 samples on real wafer are tested and show good practical feasibility of the proposed method.

• JSTS:Journal of Semiconductor Technology and Science
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• v.1 no.1
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• pp.15-19
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• 2001

Current leakage is the major failure mode of semiconductor device characteristic failures. Conventionally, failures such as short circuit breaks and gate breakdowns have been analyzed and the detected causes have been reflected in the fabrication process. By using a wafer-level emission-leakage failure analysis method (in-line QC), we analyzed leakage mode failure, which is the major failure detected during the probe inspection process for LSIs, typically DRAMs and CMOS logic LSIs. We have thus developed a new technique that copes with the critical structural failures and random failures that directly affect probe yields.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.793-796
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• 2005

In this paper, we propose a method which can improve uniformity of a miniaturized electron beam array for inspection of very small pattern with high speed using vertical interconnection. This method enables the individual control of columns so that it can reduce the deviation of beam current, beam size, scan range and so on. The test device that used vertical interconnection method was fabricated by multiple wafer bonding and metal reflow. Two silicon and one glass wafers were bonded and metal interconnection by melting of electroplated AuSn was performed. The contact resistance was under $10{\Omega}$.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.1101-1106
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• 2005

The purpose of this study was to develop a process management system to manage ingot fabrication and the quality of the ingot. The ingot is the first manufactured material of wafers. Operating data (trace parameters) were collected on-line but quality data (measurement parameters) were measured by sampling inspection. The quality parameters were applied to evaluate the quality. Thus, preprocessing was necessary to extract useful information from the quality data. First, statistical methods were employed for data generation, and then modeling was accomplished, using the generated data, to improve the performance of the models. The function of the models is to predict the quality corresponding to the control parameters. The dynamic polynomial neural network (DPNN) was used for data modeling that used the ingot fabrication data.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.555-556
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• 2008

본 연구에서는 레이저빔 투과를 이용한 본딩 웨이퍼 검사 방법을 제안하고 검사 장치를 설계 구현하였다. 1064nm 파장에서의 정상웨이퍼를 일정한 비율로 투과 하였다. 본딩 불량으로 인한 웨이퍼의 기공은 두께에 따라 투과율이 현저하게 변화하여 기공 부분을 검출하였다. 이러한 기공은 두께의 변화가 있으며 광량의 변화하는 부분이 에어갭으로 인식 카메라로 쉽게 구분이 가능하였다.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.7 no.1
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• pp.47-52
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• 2008

We present a 3-D profiler specially devised for the profile measurement of rough surfaces that are difficult to be measured with conventional non-contact interferometer. The profiler comprises multiple two-point-diffraction sources made of single-mode optical fibers. Test measurement proves that the proposed profiler is well suited for the warpage inspection of microelectronics components with rough surface, such as unpolished backsides of silicon wafers and plastic molds of integrated-circuit chip package.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.11
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• pp.2085-2092
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• 2016

One of the most important properties of the IC substrate is that it should be uniform over large areas. Among the various physical approaches of wafer defect characterization, special attention is to be payed to the infrared techniques of inspection. In particular, a high spatial resolution, near infrared absorption method has been adopted to directly observe defects in semi-insulating GaAs. This technique, which relies on the mapping of infrared transmission, is both rapid and non-destructive. This method demonstrates in a direct way that the infrared images of GaAs crystals arise from defect absorption process. A new interpretation is presented for the observed reversal of contrast in the infrared absorption of nonuniformly distributed deep centers, related to EL2, in semi-insulating GaAs. The low temperature photoquenching experiment has demonstrated in a direct way that the contrast inverse images of GaAs wafers arise from both absorption and scattering mechanisms rather than charge re-distribution or local variation of bandgap.

• Journal of the Korean Society for Precision Engineering
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• v.30 no.7
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• pp.702-708
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• 2013

The white-light scanning interferometer (WSI) is an effective optical measurement system for high-precision industries (e.g., flat-panel display and electronics packaging manufacturers) and semiconductor manufacturing industries. Its major disadvantages include a slow image-capturing speed for interferogram acquisition and a high computational cost for peak-detection on the acquired interferogram. Here, a WSI system is proposed for the semiconductor inspection process. The new imaging acquisition technique uses an 'on-the-fly' imaging system. During the vertical scanning motion of the WSI, interference fringe images are sequentially acquired at a series of pre-defined lens positions, without conventional stepwise motions. To reduce the calculation time, a parallel computing method is used to link multiple personal computers (PCs). Experiments were performed to evaluate the proposed high-speed WSI system.