• 한국정밀공학회지
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• 제16권3호통권96호
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• pp.78-83
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• 1999

The bonding interface is dependent on the properties of surfaces prior to SDB(silicon wafer direct bonding). In this paper, we prepared silicon surfaces in several chemical solutions, and annealed bonding wafers which were combined with thermally oxidized wafers and bare silicon wafers in the temperature range of $600{\times}1000^{\circ}C$. After bonding, the bonding interface is investigated by an infrared(IR) topography system which uses the penetrability of infrared through silicon wafer. Using this procedure, we observed intrinsic bubbles at elevated temperatures. So, we verified that these bubbles are related to cleaning and drying conditions, and the interface oxides on silicon wafer reduce the formation of intrinsic bubbles.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1999년도 춘계학술대회 논문집
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• pp.370-373
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• 1999

Si direct bonding (SDB) technology is very attractive for both Si-on-insulator(SOI) electric devices and MEMS applications because of its stress free structure and stability. This paper presents on- pre treatment conditions in Si wafer direct bonding, The paper resents on pre-bonding according to HF pre-treatment conditions in Si wafer direct bonding. The characteristics of bonded sample were measured under different bonding conditions of HF concentration, applied pressure and annealing temperature(200~ 100$0^{\circ}C$) after pre-bonding. The bonding strength was evaluated by tensile strength method. The bonded interface and the void were analyzed by using SEM and IR camera, respectively, Components existed in the interlayer were analyzed by using FT-IR. The bond strength depends on the HF pre-treatment condition before pre-bonding(Min 2.4kgf/$\textrm{cm}^2$~ Max : 14.kgf/$\textrm{cm}^2$)

• 한국전기전자재료학회논문지
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• 제16권5호
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• pp.365-371
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• 2003

We prepared silicon on insulator(SOI) wafer pairs of Si/1800${\AA}$ -SiO$_2$ ∥ 1800${\AA}$ -SiO$_2$/Si using water direct bonding method. Wafer pairs bonded at room-temperature were annealed by a normal furnace system or a fast linear annealing(FLA) equipment, and the micro-structure of bonding interfaces for each annealing method was investigated. Upper wafer of bonded pairs was polished to be 50 $\mu\textrm{m}$ by chemical mechanical polishing(CMP) process to confirm the real application. Defects and bonding area of bonded water pairs were observed by optical images. Electrical and mechanical properties were characterized by measuring leakage current for sweeping to 120 V, and by observing the change of wafer curvature with annealing process, respectively. FLA process was superior to normal furnace process in aspects of bonding area, I-V property, and stress generation.

• 한국재료학회지
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• 제8권10호
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• pp.890-897
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• 1998

n-InP(001)기판과 PECVD법으로 ${Si}_3N_4$(200nm)막이 성장된 InP 기판사이의 direct wafer bonding을 분석하였다. 두 기판을 접촉시켰을 때 이들 사이의 결합력에 크게 영향을 주는 표면 상태를 접촉각 측정과 AFM을 통해서 분석하였다. InP 기판은 $50{\%}$ 불산용액으로 에칭하였을 때 접촉각이 $5^{\circ}$, RMS roughness는 $1.54{\AA}$이었다. ${Si}_3N_4$는 암모니아수 용액으로 에칭하였을 때 RMS roughness가 $3.11{\AA}$이었다. Inp 기판과 ${Si}_3N_4$/InP를 각각 $50{\%}$ 불산 용액과 암모니아수 용액에 에칭한 후 접촉시켰을 때 상당한 크기의 초기 겹합력을 관찰할 수 있었다. 기계적으로 결합된 시편을 $580^{\circ}C$-$680^{\circ}C$, 1시간동안 수소 분위기와 질소분우기에서 열처리하였다. SAT(Scanning Acoustic Tomography)측정으로 두 기판 사이의 결합여부를 확인하였다. shear force로 측정한 InP 기판과 ${Si}_3N_4$/InP사이의 결합력은 ${Si}_3N_4$/InP 계면의 결합력만큼 증가되었다. TEM과 AES를 이용해서 di-rect water bonding 계면과 PECVD계면을 분석하였다.

• 한국세라믹학회지
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• 제36권8호
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• pp.863-870
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• 1999

SOI(silicon on insulafor) was fabricated through the direct bonding using (100) Si wafer and 4$^{\circ}$off (100) Si wafer to investigate the stacking faults in silicon at the Si/SiO2 oxidized and bonded interface. The treatment time of wafer surface using MSC-1 solution was varied in order to observe the effect of cleaning on bonding characteristics. As the MSC-1 treating time increased surface hydrophilicity was saturated and surface microroughness increased. A comparison of surface hydrophilicity and microroughness with MSC-1 treating time indicates that optimum surface modified condition for time was immersed in MSC-1 for 2 min. The SOI structure directly bonded using (100) Si wafer and 4$^{\circ}$off (100) Si wafer at the room temperature were annealed at 110$0^{\circ}C$ for 30 min. Then the stacking faults at the bonding and oxidation interface were examined after the debonding. The results show that there were anomalies in the gettering of the stacking faults at the bonded region.

• 한국전기전자재료학회논문지
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• 제16권10호
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• pp.859-864
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• 2003

We prepared SOI(silicon-on-insulator) wafer pairs of Si II SiO$_2$/Si$_3$N$_4$ II Si using wafer direct bonding with an electric furnace annealing(EFA), a fast linear annealing(FLA), and a rapid thermal annealing(RTA), respectively, by varying the annealing temperatures at a given annealing process. We measured the bonding area and the bonding strength with processes. EFA and FLA showed almost identical bonding area and theoretical bonding strength at the elevated temperature. RTA was not bonded at all due to warpage, We report that FLA process was superior to other annealing processes in aspects of surface temperature, annealing time, and bonding strength.

• 한국재료학회지
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• 제16권10호
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• pp.652-655
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• 2006

A direct wafer bonding process necessary for GaAs-on-insulator (GOI) fabrication with high thermal annealing temperatures was studied by using PECVD oxides between gallium arsenide and silicon wafers. In order to apply some uniform pressure on initially-bonded wafer pairs, a graphite sample holder was used for wafer bonding. Also, a tool for measuring the tensile forces was fabricated to measure the wafer bonding strengths of both initially-bonded and thermally-annealed samples. GaAs/$SiO_2$/Si wafers with 0.5-$\mu$m-thick PECVD oxides were annealed from $100^{\circ}C\;to\;600^{\circ}C$. Maximum bonding strengths of about 84 N were obtained in the annealing temperature range of $400{\sim}500^{\circ}C$. The bonded wafers were not separated up to $600^{\circ}C$. As a result, the GOI wafers with high annealing temperatures were demonstrated for the first time.

• 마이크로전자및패키징학회지
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• 제20권1호
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• pp.7-13
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• 2013

3D 적층 IC 개발을 위한 본딩 기술의 현황에 대해 알아보았다. 실리콘 웨이퍼를 본딩하여 적층한 후 배선 공정을 진행하는 wafer direct bonding 기술보다는 배선 및 금속 범프를 먼저 형성한 후 금속 본딩을 통해 웨이퍼를 적층하는 공정이 주로 연구되고 있다. 일반적인 Cu 열압착 본딩 방식은 높은 온도와 압력을 필요로 하기 때문에 공정온도와 압력을 낮추기 위한 연구가 많이 진행되고 있으며, 그 가운데서 Ar 빔을 조사하여 표면을 활성화 시키는 SAB 방식과 실리콘 산화층과 Cu를 동시에 본딩하는 DBI 방식이 큰 주목을 받고 있다. 국내에서는 Cu 열압착 방식을 이용한 웨이퍼 레벨 적층 기술이 현재 개발 중에 있다.

• 한국전기전자재료학회논문지
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• 제15권6호
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• pp.479-485
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• 2002

We have investigated the effects of various wafers cleaning on glass/Si bonding using 4 inch Pyrex glass wafers and 4 inch silicon wafers. The various wafer cleaning methods were examined; SPM(sulfuric-peroxide mixture, $H_2SO_4:H_2O_2$ = 4 : 1, $120^{\circ}C$), RCA(company name, $NH_4OH:H_2O_2:H_2O$ = 1 : 1 : 5, $80^{\circ}C$), and combinations of those. The best room temperature bonding result was achieved when wafers were cleaned by SPM followed by RCA cleaning. The minimum increase in surface roughness measured by AFM(atomic force microscope) confirmed such results. During successive heat treatments, the bonding strength was improved with increased annealing temperatures up to $400^{\circ}C$, but debonding was observed at $450^{\circ}C$. The difference in thermal expansion coefficients between glass and Si wafer led debonding. When annealed at fixed temperatures(300 and $400^{\circ}C$), bonding strength was enhanced until 28 hours, but then decreased for further anneal. To find the cause of decrease in bonding strength in excessively long annealing time, the ion distribution at Si surface was investigated using SIMS(secondary ion mass spectrometry). tons such as sodium, which had been existed only in glass before annealing, were found at Si surface for long annealed samples. Decrease in bonding strength can be caused by the diffused sodium ions to pass the glass/si interface. Therefore, maximum bonding strength can be achieved when the cleaning procedure and the ion concentrations at interface are optimized in glass/Si wafer direct bonding.

• 반도체디스플레이기술학회지
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• 제20권4호
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• pp.171-176
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• 2021

Die-to-wafer (D2W) hybrid bonding in the multilayer semiconductor manufacturing process is one of wafer direct bonding, and various studies are being conducted around the world. A noteworthy point in the current die-to-wafer process is that a lot of voids occur on the bonding surface of the die during bonding. In this study, as a suggested method for removing voids generated during the D2W hybrid bonding process, a flexible mechanism for implementing convex for die bonding to be applied to the bond head is proposed. In addition, modeling of flexible mechanisms, analysis/design/control/evaluation of static/dynamics properties are performed. The proposed system was controlled by capacitive sensor (lion precision, CPL 290), piezo actuator (P-888,91), and dSpace. This flexure mechanism implemented a working range of 200 ㎛, resolution(3σ) of 7.276nm, Inposition(3σ) of 3.503nm, settling time(2%) of 500.133ms by applying a reverse bridge type mechanism and leaf spring guide, and at the same time realized a maximum step difference of 6 ㎛ between die edge and center. The results of this study are applied to the D2W hybrid bonding process and are expected to bring about an effect of increasing semiconductor yield through void removal. In addition, it is expected that it can be utilized as a system that meets the convex variable amount required for each device by adjusting the elongation amount of the piezo actuator coupled to the flexible mechanism in a precise unit.