• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.3
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• pp.196-203
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• 2004

A three-dimensional (3D) IC technology platform is presented for high-performance, low-cost heterogeneous integration of silicon ICs. The platform uses dielectric adhesive bonding of fully-processed wafer-to-wafer aligned ICs, followed by a three-step thinning process and copper damascene patterning to form inter-wafer interconnects. Daisy-chain inter-wafer via test structures and compatibility of the process steps with 130 nm CMOS sal devices and circuits indicate the viability of the process flow. Such 3D integration with through-die vias enables high functionality in intelligent wireless terminals, as vertical integration of processor, large memory, image sensors and RF/microwave transceivers can be achieved with silicon-based ICs (Si CMOS and/or SiGe BiCMOS). Two examples of such capability are highlighted: memory-intensive Si CMOS digital processors with large L2 caches and SiGe BiCMOS pipelined A/D converters. A comparison of wafer-level 3D integration 'lith system-on-a-chip (SoC) and system-in-a-package (SiP) implementations is presented.

• Journal of the Microelectronics and Packaging Society
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• v.10 no.3
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• pp.57-65
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• 2003

In this study, we carry out reliability tests and investigate the failure mechanisms of the anodically bonded wafer level vacuum packaging (WLVP) MEMS gyroscope sensor. There are three failure mechanisms of WLVP: leakage, permeation and out-gassing. The leakage is caused by small dimension of the leak channel through the bonding interface and internal defects. The larger bonding width and the use of single crystalline silicon can reduce the leak rate. Silicon and glass wafer itself generates a large amount of outgassing including $H_2O$, $C_3H_5$, $CO_2$, and organic gases. Epi-poly wafer generates 10 times larger amount of outgassing than SOI wafer. The sandblasting process in the glass increases outgassing substantially. Outgassing can be minimized by pre-baking of the wafer in the vacuum oven before bonding process. An optimum pre-baking temperature of the wafers would be between $400^{\circ}C$ and $500^{\circ}C$.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.183-184
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• 2007

A 40 Gb/s transimpedance amplifier IC was designed and fabricated with a InP/InGaAs HBTs technology. In this study, we interconnect 40Gbps trans impedance amplifier IC to a duroid substrate by a flip chip bonding instead of conventional wire bonding for interconnection. For flip chip bonding, we developed fine pitch bump with the $70{\mu}m$ diameter and $150{\mu}m$ pitch using WLP process. To study the effect of WLP, electrical performance was measured and analyzed in wafer and package module using WLP. The Small signal gains in wafer and package module were 7.24 dB and 6.93dB respectively. The difference of small signal gain in wafer and package module was 0.3dB. This small difference of gain is due to the short interconnection length by bump. The characteristics of return loss was under -10dB in both wafer and module. So, WLP process can be used for millimeter wave GaAs MMIC with the fine pitch pad and duroid substrate can be used in flip chip bonding process.

• Korean Journal of Materials Research
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• v.14 no.5
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• pp.315-321
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• 2004

The void evolution in direct bonding process of $Si/Si_3$$N_4$ ∥ $SiO_2$/Si silicon wafer pairs has been investigated with an infrared camera. The voids that formed in the premating process grew in the conventional furnace annealing process at a temperature of $600^{\circ}C$. The voids are never shrunken even with the additional annealing process at the higher temperatures. We observed that the voids became smaller and disappeared with sequential scanning by our newly proposed fast linear annealing(FLA). FLA irradiates the focused line-shape halogen light on the surface while wafer moves from one edge to the other. We also propose the void shrinking mechanism in FLA with the finite differential method (FDM). Our results imply that we may eliminate the voids and enhance the yield for the direct bonding of wafer pairs by employing FLA.

• Journal of Sensor Science and Technology
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• v.15 no.1
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• pp.58-64
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• 2006

In this study, we describe a low-temperature wafer-level thermocompression bonding using electroplated gold seal line and bonding pads by electroplating method for RF-MEMS devices. Silicon wafers, electroplated with gold (Au), were completely bonded at $320^{\circ}C$ for 30 min at a pressure of 2.5 MPa. The through-hole interconnection between the packaged devices and external terminal did not need metal filling process and was made by gold films deposited on the sidewall of the throughhole. This process was low-cost and short in duration. Helium leak rate, which is measured to evaluate the reliability of bonded wafers, was $2.7{\pm}0.614{\times}10^{-10}Pam^{3}/s$. The insertion loss of the CPW packaged was $-0.069{\sim}-0.085\;dB$. The difference of the insertion loss between the unpackaged and packaged CPW was less than -0.03. These values show very good RF characteristics of the packaging. Therefore, gold thermocompression bonding can be applied to high quality hermetic wafer level packaging of RF-MEMS devices.

• The Korean Journal of Ceramics
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• v.3 no.1
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• pp.18-20
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• 1997

The fabrication process of silicon-diamond(SOD) structure wafer were studied. Microwave plasma chemical vapor deposition (MWPCVD) and annealing technology were used to synthesize diamond film with high resistivity and thermal conductivity. Bonding and etchback silicon-on-diamond (BESOD) were utilized to form supporting substrate and single silicon thin layer of SOD wafer. At last, a SOD structure wafer with 0.3~1$\mu\textrm{m}$ silicon film and 2$\mu\textrm{m}$ diamond film was prepared. The characteristics of radiation for a CMOS integrated circuit (IC) fabricated by SOD wafer were studied.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2004.11a
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• pp.11-11
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• 2004

• Journal of the Microelectronics and Packaging Society
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• v.20 no.2
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• pp.47-51
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• 2013

Chemical mechanical polishing (CMP) has become one of the key processes in wafer level stacking technology for 3D stacked IC. In this study, two-step CMP process was proposed to polish $Cu/SiO_2$ hybrid bonding surface, that is, Cu CMP was followed by $SiO_2$ CMP to minimize Cu dishing. As a result, Cu dishing was reduced down to $100{\sim}200{\AA}$ after $SiO_2$ CMP and surface roughness was also improved. The bonding interface showed no noticeable dishing or interface line, implying high bonding strength.

• Korean Journal of Materials Research
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• v.15 no.9
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• pp.613-619
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• 2005

The ever increasing popularity and acceptance in the market place of portable systems, such as cell phones, PDA, notebook PC, etc., are fueling effects in further miniaturizing and lowering power consumption in these systems. The dynamic power consumption due to the CPU activities and the static power consumption due to leakage currents are two major sources of power consumption. Smaller devices and a lower de voltage lead to reducing the power requirement, while better insulation and isolation of devices lead to reducing leakage currents. All these can be harnessed in the SOI (silicon-on-insulator) technology. In this study, the key aspects of the SOI technology, mainly device electrical properties and device processing steps, are briefly reviewed. The interesting materials issues, such as SOI structure formation and SOI wafer fabrication methods, are then surveyed. In particular, the recent technological innovations in two major SOI wafer fabrication methods, namely wafer bonding and SIMOX, are explored and compared in depth. The results of the study are nixed in that, although the quality of the SOI structures has shown great improvements, the processing steps are still found to be too complex. Between the two methods, no clear winner has yet emerged in terms of the product quality and cost considerations.

• Transactions on Electrical and Electronic Materials
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• v.1 no.1
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• pp.6-11
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• 2000

The hydrogen plasma treatment of silicon wafers in the reactive ion-etching mode was studied for the application to silicon-on-insulator wafers which were prepared using the wafer bonding technique. The chemical reactions of hydrogen plasma with surface were used for both surface activation and removal of surface contaminants. As a result of exposure of silicon wafers to the plasma, an active oxide layer was found on the surface. This layer was rendered hydrophilic. The surface roughness and morphology were examined as functions of the plasma exposing time and power. In addition, the surface became smoother with the shorter plasma exposing time and power. The value of initial surface energy estimated by the crack propagation method was 506 mJ/㎡, which was up to about three times higher as compared to the case of conventional direct using the wet RCA cleaning method.