마이크로전자및패키징학회지 (Journal of the Microelectronics and Packaging Society)

  • 제20권2호
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  • Pages.47-51
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  • 2013
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  • 1226-9360(pISSN)
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  • 2287-7525(eISSN)
한국마이크로전자및패키징학회 (The Korean Microelectronics and Packaging Society)
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웨이퍼 레벨 Cu 본딩을 위한 Cu/SiO2 CMP 공정 연구

Cu/SiO2 CMP Process for Wafer Level Cu Bonding

  • 이민재 (서울과학기술대학교 기계시스템디자인공학과) ;
  • 김사라은경 (서울과학기술대학교 NID 융합기술대학원) ;
  • 김성동 (서울과학기술대학교 기계시스템디자인공학과)
  • Lee, Minjae (Dept. of Mechanical System Design Eng., Seoul National University of Science and Technology) ;
  • Kim, Sarah Eunkyung (Graduate School of NID Fusion Technology, Seoul National University of Science and Technology) ;
  • Kim, Sungdong (Dept. of Mechanical System Design Eng., Seoul National University of Science and Technology)
  • 투고 : 2013.06.18
  • 심사 : 2013.06.25
  • 발행 : 2013.06.30
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초록

본 연구에서는 웨이퍼 레벨 Cu 본딩을 이용한 3D 적층 IC의 개발을 위해 2단계 기계적 화학적 연마법(CMP)을 제안하고 그 결과를 고찰하였다. 다마신(damascene) 공정을 이용한 $Cu/SiO_2$ 복합 계면에서의 Cu dishing을 최소화하기 위해 Cu CMP 후 $SiO_2$ CMP를 추가로 시행하였으며, 이를 통해 Cu dishing을 $100{\sim}200{\AA}$까지 낮출 수 있었다. Cu 범프의 표면거칠기도 동시에 개선되었음을 AFM 관찰을 통해 확인하였다. 2단 CMP를 적용하여 진행한 웨이퍼 레벨 Cu 본딩에서는 dishing이나 접합 계면이 관찰되지 않아 2단 CMP 공정이 성공적으로 적용되었음을 확인할 수 있었다.

Chemical mechanical polishing (CMP) has become one of the key processes in wafer level stacking technology for 3D stacked IC. In this study, two-step CMP process was proposed to polish $Cu/SiO_2$ hybrid bonding surface, that is, Cu CMP was followed by $SiO_2$ CMP to minimize Cu dishing. As a result, Cu dishing was reduced down to $100{\sim}200{\AA}$ after $SiO_2$ CMP and surface roughness was also improved. The bonding interface showed no noticeable dishing or interface line, implying high bonding strength.

키워드

참고문헌

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피인용 문헌

  1. Effects of forming gas plasma treatment on low-temperature Cu–Cu direct bonding vol.55, pp.6S3, 2016, https://doi.org/10.7567/JJAP.55.06JC02
  2. Wafer level Cu–Cu direct bonding for 3D integration vol.137, 2015, https://doi.org/10.1016/j.mee.2014.12.012