• 제목/요약/키워드: voltage standard

검색결과 977건 처리시간 0.026초

초고압 송전선로의 자계크기 실측과 해석 (Measurement and Analysis of the Magnetic Fields Magnitude under High Voltage Transmission Lines)

  • 조성배;이은웅;이민명
    • 대한전기학회:학술대회논문집
    • /
    • 대한전기학회 1998년도 하계학술대회 논문집 E
    • /
    • pp.1583-1585
    • /
    • 1998
  • EMF measurements for the selected lines by a kinds of tower configurations conductors among 154kV, 345kV transmission lines which are a standard forms of high voltage transmission line in Domestic are performed at the field. Based on these measurings, Co-relation of both the Power current and the magnetic field strength is studed. compared of measured and calculated magnetic magnitude. and Using the measured equation obtained from field measuring, Magnetic field exposure value occurring under T/L for one year(1997) is presented.

  • PDF

실리콘 액정표시 장치 시스템을 위한 00.5μm 이중 게이트 고전압 CMOS 공정 연구 (A Study on the 0.5μm Dual Gate High Voltage CMOS Process for Si Liquid Display System)

  • 송한정
    • 한국전기전자재료학회논문지
    • /
    • 제15권12호
    • /
    • pp.1021-1026
    • /
    • 2002
  • As the development of semiconductor process technology continue to advance, ICs continue their trend toward higher performance low power system-on-chip (SOC). These circuits require on board multi power supply. In this paper, a 0.5 ㎛ dual date oxide CMOS Process technology for multi-power application is demonstrated. 5 V and 20 V devices fabricated by proposed process is measured. From 5 V devices using dual gate precess, we got almost the same characteristics as are obtained from standard 5 V devices. And the characteristics of the 20 V device demonstrates that 3 ㎛ devices with minimum gate length are available without reliability degradation. Electrical parameters in minimum 3 ㎛ devices are 520 ㎂/㎛ current density, 120 ㎷ DIBL, 24 V BV for NMOS and ,350 ㎂/㎛ current density, 180 ㎷ DIBL, 26 V BV for PMOS, respectively.

전철선로 임피던스계산에 관한 연구 (A Study on Electrified Railway Traction System Impedance Calculation)

  • 이춘배;김왕곤;이종우
    • 한국철도학회:학술대회논문집
    • /
    • 한국철도학회 2004년도 추계학술대회 논문집
    • /
    • pp.1407-1412
    • /
    • 2004
  • Impedance calculations of electric railway traction systems is essential to define characteristics and to design it. The self impedance is defined voltage drop rate per unit length, the mutual impedance is represented as a voltage induced to transmission line from transmission line. The self and the mutual impedance are influenced by ground return currents. The earth is considered as a semi-infinitely extended non-ideal conductor. The current of transmission line produces earth current induced magnetically and it flow through a path having minimum impedance. Carson proposed the impedance calculation formula using wave equations and magnetic field equations. Though the formula have an improper equation, that is still used as a standard impedance calculation method. This paper introduced an impedance calculation method that the complex depth of earth return method assumes that the current in conductor returns through an imagined earth depth path located directly under original conductor at a depth of. In this paper, we showed that this proposed method has a closed form and is easier than Carson's.

  • PDF

CMOS 아날로그 셀 라이브레이 설계에 관한 연구-CMOS 온-칩 전류 레퍼런스 회로 (A study on a CMOS analog cell-library design-A CMOS on-chip current reference circuit)

  • 김민규;이승훈;임신일
    • 전자공학회논문지A
    • /
    • 제33A권4호
    • /
    • pp.136-141
    • /
    • 1996
  • In this paper, a new CMOS on-chip current reference circit for memory, operational amplifiers, comparators, and data converters is proposed. The reference current is almost independent of temeprature and power-supply variations. In the proposed circuit, the current component with a positive temeprature coefficient cancels that with a negative temperature coefficient each other. While conventional curretn and voltage reference circuits require BiCMOS or bipolar process, the presented circuit can be integrated on a single chip with other digiral and analog circits using a standard CMOS process and an extra mask is not needed. The prototype is fabricated employing th esamsung 1.0um p-well double-poly double-metal CMOS process and the chip area is 300um${\times}$135 um. The proposed reference current circuit shows the temperature coefficient of 380 ppm/.deg. C with the temperature changes form 30$^{\circ}C$ to 80$^{\circ}C$, and the output variation of $\pm$ 1.4% with the supply voltage changes from 4.5 V to 5.5 V.

  • PDF

수도사업장 고조파 측정, 분석을 통한 관리기준 만족여부 조사 (To examine of management standard by the harmonics measured and analyzed in water supply field)

  • 홍성택;이은춘;신강욱;임재일
    • 대한전기학회:학술대회논문집
    • /
    • 대한전기학회 2003년도 하계학술대회 논문집 A
    • /
    • pp.296-298
    • /
    • 2003
  • At the water supply field, high voltage induction motor is main facility of a load equipment. The motor is often out of order and its noise, generated heat, loss etc occured occasionally. especially, transmission motor for flux control generates an amount of the harmonics then have a bad influence upon the electric power system. In this study, to analyze the total harmonics distortion of the water supply field receiving high voltage, the harmonics measured and analyzed using the PQA(Power Quality Analyzer) according to the electric power system and electrical load and the reduction method presented.

  • PDF

유한요소법에 의한 고압절연애자의 오손특성설계법의 개발 (Study on design technique of high voltage insulators in contaminated environment using finite element method.)

  • 황영문;이일천
    • 전기의세계
    • /
    • 제29권10호
    • /
    • pp.653-659
    • /
    • 1980
  • The paper describes a new technique for the shape design of a bell-type porcelain locke insulator in contaminated environment. Early studies on the contamination performance of insulators indicated the need for an improvable shape to provide adequate insulation strength at normal operating voltages. In this paper, under lightly and heavily contaminated site severity, the variation of voltage distribution to leakage path at insulator surfaces analyzed by the complex admittance matrix using finite element method. By this results, the improvement of shape of insulators could be approached to the available condition in contaminated environments. In applicating to compare a standard disc type with a fog disc type insulator, this design technique is valid.

  • PDF

용담댐 발전소 접지설계를 위한 대지비저항 모델링 및 접지저항 추정 (Earth Resistivity Modelling and Grounding Resistance Estimation for Yongdam Dam Power Station Grounding Design)

  • 오민환;김형수;김종득
    • 대한전기학회:학술대회논문집
    • /
    • 대한전기학회 1998년도 하계학술대회 논문집 C
    • /
    • pp.1188-1191
    • /
    • 1998
  • Detailed estimation of subsurface resistivity distribution and accurate estimation of actual fault current coming into the grounding system are indispensible to optimun grounding system design. Especially, it is essential for efficient grounding design to estimate subsurface resistivity distribution quantitatively and logically. Accurate estimation of subsurface resistivity distribution has an absolute influence on calculating touch voltage, step voltage and ground potential rise (GPR) which are related with grounding design standard for human safety. In this study, thirty-three electrical sounding surveys were made in Yongdam Power Station to obtain detailed subsurface resistivity distribution and the sounding data were interpreted quantitatively using multi-layered model. The results of the quantitative resistivity models were adopted practically to calculate grounding resistance values. Analytical asymptotic equations and CDEGS program were used in grounding resistance calculation and the results were compared and reviewed in the study.

  • PDF

NAND 전하트랩 플래시메모리를 위한 p채널 SONOS 트랜지스터의 특성 (The Characteristics of p-channel SONOS Transistor for the NAND Charge-trap Flash Memory)

  • 김병철;김주연
    • 한국전기전자재료학회논문지
    • /
    • 제22권1호
    • /
    • pp.7-11
    • /
    • 2009
  • In this study, p-channel silicon-oxide-nitride-oxide-silicon(SONOS) transistors are fabricated and characterized as an unit cell for NAND flash memory. The SONOS transistors are fabricated by $0.13{\mu}m$ low power standard logic process technology. The thicknesses of gate insulators are 2.0 nm for the tunnel oxide, 1.4 nm for the nitride layer, and 4.9 nm for the blocking oxide. The fabricated SONOS transistors show low programming voltage and fast erase speed. However, the retention and endurance of the devices show poor characteristics.

용액공정을 이용한 ZnSnO 산화물 반도체 박막 트랜지스터에서 Mg 첨가에 따른 영향 (Electrical Properties of Mg Doped ZnSnO TFTs Fabricated by Solution-process)

  • 최준영;박기호;김상식;이상렬
    • 한국전기전자재료학회논문지
    • /
    • 제24권9호
    • /
    • pp.697-700
    • /
    • 2011
  • Thin-film transistors(TFTs) with magnesium zinc tin oxide(MZTO) channel layer are fabricated by solution-process. The threshold voltage (Vth) shifted toward positive directly with increasing Mg contents in MZTO system. Because the Mg has a lower standard electrode potential (SEP) than Sn, Zn, thus degenerate the oxygen vacancy ($V_O$). As a result, the Mg act as carrier suppressor and oxygen binder in the MZTO as well as a Vth controller.

퓨즈가 내장된 엘보접속재의 설계 (Design of Fuse Mounted Elbow Connector)

  • 최경선;이철호;송일근;권태종;권영복;한명관
    • 한국전기전자재료학회:학술대회논문집
    • /
    • 한국전기전자재료학회 2000년도 추계학술대회 논문집
    • /
    • pp.383-386
    • /
    • 2000
  • Fuse mounted elbow connector used for pad mounted transformer was designed and investigated. Requirements of electrical ratings such as partial discharge, ac withstand voltage and impulse voltage and material properties were proposed in accordance with IEEE 386 and pre-standard (PS) 147-219∼229 of KEPCO. The connector can be jointed with pad mounted transformer and current limiting fuse which is installed inside of the connector easily replaced with new one in the case of breakdown of the fuse. Electric field analysis was also introduced in other to verify the reliability of the design.

  • PDF