• ETRI Journal
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• v.32 no.4
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• pp.520-529
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• 2010

In this paper, we present a low-voltage low-dropout voltage regulator (LDO) for a system-on-chip (SoC) application which, exploiting the multiplication of the Miller effect through the use of a current amplifier, is frequency compensated up to 1-nF capacitive load. The topology and the strategy adopted to design the LDO and the related compensation frequency network are described in detail. The LDO works with a supply voltage as low as 1.2 V and provides a maximum load current of 50 mA with a drop-out voltage of 200 mV: the total integrated compensation capacitance is about 40 pF. Measurement results as well as comparison with other SoC LDOs demonstrate the advantage of the proposed topology.

• Proceedings of the KIPE Conference
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• 2008.06a
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• pp.574-576
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• 2008

Now there are two types Non-contact compensation AC automatic voltage regulator (A.V.R). One is transformer compensation regulator, whose principle is the combination of multiple compensation transformers, do the compensation by turning on and off the connections of the transformer through the multi-full bridge circuit. This method removed the mechanical drive and contacts, which increases the life and the dynamic performance of the A.V.R. However, the compensation is multilevel, and it needs many compensation transformers and switches, the circuit is complex, the compensation precision is low. Another type is PWM switch AC regulator, whose principle is getting the AC voltage from the input, then induce the AC compensation voltage through commutating and high frequency PWM transforming, and phase tracking. Here the compensation is step-less, the compensation precision is high, and the response is fast. But the circuit is complex, and it needs an inverse compensation transformer, which is difficult to realize high-power applications. In this paper, it shows an Automatic Voltage Regulator which use high frequency PWM inverter do compensation. This A.V.R has the function as the custom-power, which make the performance of the power supply in a high level.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.2
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• pp.123-129
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• 2016

In this paper, results of produced PCU(Power Control Unit) prototype was showed by suggesting and maintaining optimal operation status which let the three functional modules automatically operate with its necessity by prioritizing operation process. In order to validate effectiveness of the suggested method, we produced a test PCU and examined the results. PCU consists of S3R(Sequential Switching Shunt Regulator), BCR(Battery Charge Regulator), and BDR(Battery Discharge Regulator): converting photovoltaic power into constant voltage at linked bus voltage; storing dump power in the battery which is an auxiliary energy storage device; and supplying power charged in battery to the load. To maintain its high reliability and optimal condition of these three power conversion modules, each module operates in parallel and stable bus voltage is required to be retained at all-time due to the nature of power supply for satellite.

• Proceedings of the KIEE Conference
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• 2002.07b
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• pp.1075-1077
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• 2002

This paper describes a three-phase step-down AC voltage regulator using AC chopper and auxiliary transformer which is series connected with main input. It has many advantages such as fast voltage control, high efficiency and low THD. The operation principle and PWM method of the proposed regulator are described. Experimental results show that it can be used as step-down AC voltage regulator for power saving purpose very efficiently.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.65 no.8
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• pp.1383-1391
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• 2016

This paper is concerned with applicability of a new type of controllers, called i-PID and GPI in which unknown parts of the plant are taken into account without any modeling procedure, to automatic voltage regulator (AVR) system. First, the procedure for applying i-PID and GPI algorithms to AVR system is proposed, which uses model reduction technique based on the given information of AVR. Second, simulations are given to verify their effectiveness comparing to various PID algorithms including PIDD2 which is four-term controller, that is, consisting of PID and second order derivative terms. Superior response performances of i-PID and GPI in comparison to conventional PID controllers are shown. Moreover, i-PID can highly improve the system robustness with respect to model uncertainties, especially to load variations.

• ETRI Journal
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• v.39 no.3
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• pp.373-382
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• 2017

A new internally compensated low drop-out voltage regulator based on the cascoded flipped voltage follower is presented in this paper. Adaptive biasing current and fast charging/discharging paths have been added to rapidly charge and discharge the parasitic capacitance of the pass transistor gate, thus improving the transient response. The proposed regulator was designed with standard 65-nm CMOS technology. Measurements show load and line regulations of $433.80{\mu}V/mA$ and 5.61 mV/V, respectively. Furthermore, the output voltage spikes are kept under 76 mV for 0.1 mA to 100 mA load variations and 0.9 V to 1.2 V line variations with rise and fall times of $1{\mu}s$. The total current consumption is $17.88{\mu}V/mA$ (for a 0.9 V supply voltage).

• Journal of IKEEE
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• v.27 no.3
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• pp.258-264
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• 2023

This paper proposes an LDO regulator with a built-in ESD (Electro Static Discharge) protection circuit to effectively operate and prevent destruction of the LDO (Low Drop Out) regulator according to the load current. The proposed LDO regulator can more effectively adjust the gate node voltage of the pass transistor according to the output voltage of the LDO regulator by using an additional feedback current circuit structure. In addition, it is expected to have high reliability for the ESD situation by embedding a new structure that increases the holding voltage by about 2V by reducing the current gain on the SCR loop by adding a P+ bridge to the existing ESD protection device.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.2
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• pp.186-192
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• 2012

Half-rail stacked drivers are used to reduce power consumption of the drivers for synchronous buck converters. In this paper, the stacked driver is optimized by matching the average charging and discharging currents used by high-side and low-side drivers. By matching the two currents, the average intermediate bias voltage can remain constant without the aid of the voltage regulator as long as the voltage ripple stays within the window defined by the hysteresis of the regulator. Thus the optimized driver in this paper can minimize the power consumption in the regulator. The current matching requirement yields the value for the intermediate bias voltage, which deviates from the half-rail voltage. Furthermore the required capacitance is also reduced in this design due to decreased charging current, which results in significantly reduced die area. The detailed analysis and design of the stacked driver is verified through simulations done using 5V MOSFET parameters of a typical 0.35-${\mu}m$ CMOS process. The difference in power loss between the conventional half-rail driver and the proposed driver is less than 1%. But the conventional half-rail driver has excess charge stored in the capacitor, which will be dissipated in the regulator unless reused by an external circuit. Due to the reduction in the required capacitance, the estimated saving in chip area is approximately 18.5% compared to the half-rail driver.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.11
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• pp.34-40
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• 2011

This paper presents a low-dropout (LDO) linear regulator using ultra-low output impedance buffer for frequency compensation. The proposed buffer achieves ultra low output impedance with dual shunt feedback loops, which makes it possible to improve load and line regulations as well as frequency compensation for low voltage applications. A reference control scheme for programmable output voltage of the LDO linear regulator is presented. The designed LDO linear regulator works under the input voltage of 2.5~4.5V and provides up to 300mA load current for an output voltage range of 0.6~3.3V.

• Journal of IKEEE
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• v.26 no.1
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• pp.124-128
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• 2022

Conventional LDO regulator external capacitors can reduce transient response characteristics such as overshoot and undershoot. However, the capacitorless LDO regulator proposed in this study applied body technology to the pass transistor to improve the transient response and provide excellent current drive capability. The operating conditions of the proposed LDO regulator are set to an input voltage that varies from 3.3V to 4.5V, a maximum load current of 200mA, and an output voltage of 3V. As a result of the measurement, it was found that when the load current was 100 mA, the voltage was 95 mV in the undershoot state and 105 mV in the overshoot state.