• KIEE International Transactions on Electrophysics and Applications
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• 제3C권1호
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• pp.1-4
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• 2003

This paper presents an attempt to develop probabilistic multistress life models to evaluate the lifetime characteristics of epoxy-encapsulated magnet wire with heavy build polyurethane enamel. A set of accelerated life tests were conducted over a wide range of pulsating voltages, temperatures, and frequencies. Samples of fine gauge twisted pairs of the encapsulated magnet wire were tested us-ing a pulse endurance dielectric test system. An electrical-thermal lifetime function was combined with the Weibull distribution of lifetimes. The parameters of the combined Weibull-electrical-thermal model were estimated using maximum likelihood estimation. Likewise, a generalized electrical-thermal-frequency life model was also developed. The parameters of this new model were estimated using multiple linear regression technique. It was found in this paper that lifetime estimates of the two proposed probabilistic multistress life models are good enough. This suggests the suitability of using the general electrical-thermal-frequency model to estimate the lifetime of the encapsulated magnet wire over a wide range of voltages, temperatures and pulsating frequencies.

• 조명전기설비학회논문지
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• 제16권2호
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• pp.90-97
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• 2002

본 논문에서는 철도 시스템에서 사용하는 저압 전원용 서지보호장치(surge protective devices) 규칙의 성능평가 항목 및 성능개선 방안에 대하여 고찰하였다. 먼저 철도시스템 환경과 관련된 전자기장해(electromagnetic interference) 현상을 검토하였다. 그리고 국제규격인 IEC 및 IEEE와 평가항목 및 펑가방법 등을 비교 검토하였다. 검토 결과 국내 철도관련 규격은 국제규격과 비교하여 비교하여 발견하였다. 개선방안으로 서지 보호소자 단위의 시험은 삭제하고, 규격 종류는 전원용과 신호용으로 분리하며, 서지 파형은 국제적으로 인정된 것을 사용하도록 제안하였다. 철도용 저압 서지보호장치에 대해 서지제한전압 측정 및 서지 수명시험을 국제규격에 따라 시험한 결과 만족스러운 결과를 얻었다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2004년도 추계학술대회 논문집 전기물성,응용부문
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• pp.67-69
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• 2004

ZnO varistor ceramics which were fabricated with variation of added of 0.01, 0.02, 0.03, 0.05, 0.1mol% $Nb_2O_5$ sintered at $1150^{\circ}C$. In the specimen added 0.05mol% $Nb_2O_5$, sintered density was $5.87g/cm^3$ and electrical properties were superior to any other components. The nonlinear coefficient was 75, and clamping voltage ratio was 1.40. And, endurance surge current in the specimen added 0.05mol% $Nb_2O_5$ was $6500A/cm^2$, and deviation of varistor voltage was -1.7%. As P.C.T and T.C.T environment test were succeed in all specimens, and deviation of varistor voltage in the specimen added 0.3mol% $Nb_2O_5$ was -0.81%. All specimens showed a good leakage current property in the High Temperature Continuous Load Test for 1000hr, at $85^{\circ}C$, and variation rate of the varistor voltage was -1.71%.

• 한국전기전자재료학회논문지
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• 제22권1호
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• pp.7-11
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• 2009

In this study, p-channel silicon-oxide-nitride-oxide-silicon(SONOS) transistors are fabricated and characterized as an unit cell for NAND flash memory. The SONOS transistors are fabricated by $0.13{\mu}m$ low power standard logic process technology. The thicknesses of gate insulators are 2.0 nm for the tunnel oxide, 1.4 nm for the nitride layer, and 4.9 nm for the blocking oxide. The fabricated SONOS transistors show low programming voltage and fast erase speed. However, the retention and endurance of the devices show poor characteristics.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2005년도 추계학술대회 논문집 전기기기 및 에너지변환시스템부문
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• pp.74-76
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• 2005

The SRG(Switched Reluctance Generator) consists of simple stator and rotor. The advantage of SRG is very endurance and low cost. Because of SRG have no magnetic, So we should obtain current of magnetic to stator. But in this step SRG have disadvantage. Disadvantage of SRG is more torque ripple, vibration and noise than other machines. This paper shows the simulation of SRG with 3phases, 6 stator poles and 4 rotor poles. We intpret the characteristics of SRG's constant voltage and torque ripple according to change switching angle.

• 한국수소및신에너지학회논문집
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• 제27권4호
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• pp.341-348
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• 2016

The experiments related on structure and water electrolysis performance of HALE UAV stack were conducted in this study. Anode catalyst $IrRuO_2$ was prepared by Adam's fusion methods as 2~3 nm nano sized particles, and the cathode catalyst was used as commercial product of Premetek. The MEA (membrane electrode assembly) was manufactured by decal methods, anode and anode catalytic layers were prepared by electro-spray. HALE stack was composed of 5 multi-cells as $0.2Nm^3/hr$ hydrogen production rate with hydrogen pressure as 10 bar. The water electrolysis performance was investigated at atmospheric pressure and temperature of $55^{\circ}C$. Best performance of HALE UAV stack was recorded as cell voltage efficiency as 86%.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2011년도 제40회 동계학술대회 초록집
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• pp.440-440
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• 2011

We report on the non-volatile memory characteristics of a bistable organic memory (BOM) device with Au nanoparticles (NPs) embedded in a conducting poly N-vinylcarbazole (PVK) colloids hybrid layer deposited on flexible polyethylene terephthalate (PET) substrates. Transmission electron microscopy (TEM) images show the Au nanoparticles distributed isotropically around the surface of a PVK colloid. The average induced charge on Au nanoparticles, estimated using the C-V hysteresis curve, was large, as much as 5 holes/NP at a sweeping voltage of ${\pm}3$ V. The maximum ON/OFF ratio of the current bistability in the BOM devices was as large as $1{\times}105$. The cycling endurance tests of the ON/OFF switching exhibited a high endurance of above $1.5{\times}105$ cycles and a high ON/OFF ratio of ~105 could be achieved consistently even after quite a long retention time of more than $1{\times}106$ s.

• 한국전기전자재료학회논문지
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• 제21권4호
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• pp.300-304
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• 2008

A novel characterization method was investigated to estimate the trap generation during the program /erase cycles in nand flash memory cell. Utilizing Fowler-Nordheim tunneling current, floating gate potential and oxide electric field, we established a quantitative model which allows the knowledge of threshold voltage (Vth) as a function of either program or erase operation time. Based on our model, the derived results proved that interface trap density (Nit) term is only included in the program operation equation, while both Nit and oxide trap density (Not) term are included in the erase operation equation. The effectiveness of our model was tested using 50 nm nand flash memory cell with floating gate type. Nit and Not were extracted through the analysis of Program/Erase speed with respect to the endurance cycle. Trap generation and cycle numbers showed the power dependency. Finally, with the measurement of the experiment concerning the variation of cell Vth with respect to program/erase cycles, we obtained the novel quantitative model which shows similar results of relationship between experimental values and extracted ones.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2010년도 하계학술대회 논문집
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• pp.122-122
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• 2010

A Static Induction Thyristor (SI-Thyristor) has a great potential as power semiconductor switch for pulsed power or high voltage applications with fast turn-on switching time and high switching stress endurance (di/dt, dV/dt). However, due to direct commutation between gate driver and SI-Thyristor, it is difficult to design optimal gate driver at the aspect of impedance matching for fast gate current driving into internal SI-Thyristor. Thus, to penetrate fast positive gate current into steady off state of the SI-Thyristor, it is proposed and proceeded the internal impedance calculation of the SI-Thyristor at steady off state with the gate driver while switching conditions that are indicated applied gate voltage, $V_{GK}$ and applied high voltage across anode and cathode, $V_{AK}$.

• 한국전기전자재료학회논문지
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• 제20권12호
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• pp.1017-1021
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• 2007

To implement tera bit level non-volatile memories of low power and fast operation, proving statistical reproductivity and satisfying reliabilities at the nano-scale are a key challenge. We fabricate the charge trapping nano scaled SONOS unit memories and 64 bit flash arrays and evaluate reliability and performance of them. In case of the dielectric stack thickness of 4.5 /9.3 /6.5 nm with the channel width and length of 34 nm and 31nm respectively, the device has about 3.5 V threshold voltage shift with write voltage of $10\;{\mu}s$, 15 V and erase voltage of 10 ms, -15 V. And retention and endurance characteristics are above 10 years and $10^5$ cycle, respectively. The device with LDD(Lightly Doped Drain) process shows reduction of short channel effect and GIDL(Gate Induced Drain Leakage) current. Moreover we investigate three different types of flash memory arrays.