• 전기학회논문지
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• 제62권5호
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• pp.657-662
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• 2013

A size-reduced high frequency mixer designed by adopting artificial dielectric substrate is described in this work. The artificial dielectric substrate is composed by stacking the lower substrate in which a lot of metalized via-holes exist, and upper substrate on which microstrip lines are realized. The effective dielectric constant increases due to the inserted lots of via-holes, and this may be applied to size-reduction of high frequency circuits. In this work, in order to present an application example of size-reduction for active high frequency circuits using the artificial dielectric substrate, a 8GHz single gate mixer is miniaturized and measured. It is described that the basic circuit elements for mixers such as hybrid, low pass filter, and matching networks can be replaced by the artificial dielectric substrate for size-reduction. The final mixer has 55% of size compared to the normal one. The measured average conversion gain is around 3dB which is almost similar result as the normal circuit.

• 한국소성가공학회:학술대회논문집
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• 한국소성가공학회 2003년도 추계학술대회논문집
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• pp.101-106
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• 2003

Recent electronic equipment becomes smaller, more functional, and more complex. According to these trends, LTCC(low temperature co-fired ceramic) has been emerged as a promising technology in packaging industry. It consists of multi-layer ceramic sheet, and the circuit has 3D structure. In this technology via hole formation plays an important role because it provides an electric path for the packaging interconnection network. Therefore via hole quality is very important for ensuring performance of LTCC product. Via holes are formed on the green sheet that consists of ceramic(before sintering) layer and PET(polyethylene Terephthalate) one. In this paper we found the correlation between hole quality and process condition such as ceramic thickness, and tool size. The shear behavior of double layer sheet by micro hole punching which is different from that of single layer one was also discussed.

• 소성∙가공
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• 제14권3호
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• pp.277-281
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• 2005

LTCC(Low temperature co-fired ceramic) is being recognized as a significant packaging material of electrical devices for the advantages such as relatively low temperature being needed for process, low conductor resistance and high printing resolution. In the process of LTCC electrical devices, the punched via-hole quality is one of the most important factors on the performance of the device. However, its mechanism is very complicated and optimization of the process seems difficult. In this paper, to clarify the process, via-hole punching experiments were carried out and the punched holes were examined in terms of their burr formation. The effects of thickness of PET sheet, ceramic sheet and punch-to- die clearance on via-hole quality were also discussed. Optimum process conditions are proposed and a factor $\kappa$ is introduced to express effect of the process variables.

• 한국안전학회지
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• 제27권6호
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• pp.26-30
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• 2012

It is difficult to determine the junction temperature because LED lightings are manufactured using several chips with low power. This paper reports on the finite element method of the determination of junction temperature in the GaN-based LEDs. The calculated junction temperature of the LED chip using FEM was compared with the experimentally measured data. As the results of this study, the junction temperature of LED chips with via holes is lower than that of LED chips without via hole. Therefore, the research of via hole is necessary to decrease junction temperature of LED chips.

• ETRI Journal
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• 제42권2호
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• pp.282-291
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• 2020

The study reports on the design and performance of two air-filled and two partial ethanol-filled photonic crystal fiber (PCF) structures with a tetra core for supercontinuum generation. The PCFs are nonlinear with ultra-flattened zero dispersion. Holes with smaller areas are used to create a tetra-core PCF structure. Ethanol is filled in the holes of smaller area while the larger holes of cladding region are airfilled. Optical properties including dispersion, effective mode area, confinement loss, normalized frequency, and nonlinear coefficient of the designed PCF structures are investigated via full vector finite difference time domain (FDTD) method. A PCF structure with lead silicate as wafer exhibits significantly better results than a PCF structure with silica as wafer. However, both structures report dispersion at a telecommunication wavelength corresponding to 1.55 ㎛. Furthermore, the PCF structure with lead silicate as wafer exhibits a very high nonlinear coefficient corresponding to 1375 W^-1 km^-1 at the same wavelength. This scheme can be used for optical communication systems and in optical devices by exploiting the principle of nonlinearity.

• JSTS:Journal of Semiconductor Technology and Science
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• 제8권3호
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• pp.244-250
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• 2008

An inductively coupled plasma etching process to replace an existing slower rate reactive ion etching process for $60{\mu}m$ diameter via-holes using Cl2/BCl3 gases has been investigated. Process pressure and platen power were varied at a constant ICP coil power to reproduce the RIE etched $200{\mu}m$ deep via profile, at high etch rate. Desired etch profile was obtained at 40 m Torr pressure, 950 W coil power, 90W platen power with an etch rate ${\sim}4{\mu}m$/min and via etch yield >90% over a 3-inch wafer, using $24{\mu}m$ thick photoresist mask. The etch uniformity and reproducibility obtained for the process were better than 4%. The metallized via-hole dc resistance measured was ${\sim}0.5{\Omega}$ and via inductance value measured was $\sim$83 pH.

• 한국전기전자재료학회논문지
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• 제24권3호
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• pp.234-239
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• 2011

In this study, the heat transfer capability have been improved by using via-holes in FR4 PCB, when the LED lighting is designed to solve the thermal problem. The thermal resistance and junction temperature were measured by changing the dimension of FR4 PCB and size of via hole. As a result, when the dimension was increased initially, the thermal resistance and junction temperature was decreased rapidly, the ones was stabilized after the dimension of 200 $[mm^2]$. Also, the light output was improved up to maximum 17% by formation of via-hole and expansion of dimension in FR4 PCB. Therefore, the thermal resistance and junction temperature could be improved by expansion of PCB dimension and configuration of via-hole ability.

• 마이크로전자및패키징학회지
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• 제17권3호
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• pp.79-84
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• 2010

3차원 Si 칩 패키징 공정을 위한 비아 홀(TSV: Through-Si-Via) 및 Au 시드층 형성, 전기 도금을 이용한 Cu 충전기술과 범핑 공정 단순화에 관하여 연구하였다. 비아 홀 형성을 위하여 $SF_6$ 와 $C_4F_8$ 플라즈마를 교대로 사용하는 DRIE(Deep Reactive Ion Etching) 법을 사용하여 Si 웨이퍼를 에칭하였다. 1.92 ks동안 에칭하여 직경 40 ${\mu}m$, 깊이 80 ${\mu}m$의 비아 홀을 형성하였다. 비아 홀의 옆면에는 열습식 산화법으로 $SiO_2$ 절연층을, 스퍼터링 방법으로 Ti 접합층과 Au 시드층을 형성하였다. 펄스 DC 전기도금법에 의해 비아 홀에 Cu를 충전하였으며, 1000 mA/$dm^2$ 의 정펄스 전류에서 5 s 동안, 190 mA/$dm^2$의 역펄스 조건에서 25 s 동안 인가하는 조건으로 총 57.6 ks 동안 전기도금하였다. Si 다이 상의 Cu plugs 위에 리소그라피 공정 없이 전기도금을 실시하여 Sn 범프를 형성할 수 있었으며, 심각한 결함이 없는 범프를 성공적으로 제조할 수 있었다.

• 전기학회논문지
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• 제59권11호
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• pp.2038-2042
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• 2010

In this paper, we confirmed the thermal & optical properties for improving the heat transfer coefficient by changing the via hole size and in FR4 PCB with the same area. Osram 1W power LED Package (Golden Dragon) was used and the K-factor which is relative constant between LED junction temperature and forward bias was measured with power source meter(KEITHLEY 2430) to measure the thermal resistance from PCB configuration. As results, thermal resistance in metal PCB came out to the lowest as $26 [^{\circ}C/W]$ and thermal resistance in FR4 PCB without via-holes emerged as the highest as $69 [^{\circ}C/W]$. However thermal resistance of FR4 PCB could have decreased until $32[^{\circ}C/W]$ in 0.6 mm by using the via hole. Also, the luminous flux could have improved, too.

• 한국항행학회논문지
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• 제17권6호
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• pp.658-663
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• 2013

본 논문에서는 비아 트랜지션을 이용하여 마이크로스트립 선로를 구현하고 이것을 이용하여 다층 레이어를 사용하여 링 하이브리드 결합기를 설계하였다. 여기서 사용된 트랜지션은 서로 다른 레이어에 존재하는 마이크로스트립 선로를 연결하기 위해서 비아를 사용한 샌드위치 구조이다. 컴팩트한 RF/ 마이크로웨이브 소자를 설계하기 위해서 이러한 비아를 이용한 마이크로스트립 선로의 구현은 긴 전송선로를 짧게 구현할 수 있다. 이러한 트랜지션의 유용성을 보이기 위해서 중심 주파수 2 GHz에서 링 하이브리드 결합기를 구현하였다. 그 결과 특성은 시뮬레이션과 거의 동일함을 확인하였고, 크기는 기존 것과 비교하여 50% 줄일 수 있다.