• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.26 no.4
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• pp.271-274
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• 2013

Power Metal Oxide Semiconductor Field Effect Transistor's (MOSFETs) are well known for superior switching speed, and they require very little gate drive power because of the insulated gate. In these respects, power MOSFETs approach the characteristics of an "ideal switch". The main drawback is on-resistance RDS(on) and its strong positive temperature coefficient. While this process has been driven by market place competition with operating parameters determined by products, manufacturing technology innovations that have not necessarily followed such a consistent path have enabled it. This treatise briefly examines metal oxide semiconductor (MOS) device characteristics and elucidates important future issues which semiconductor technologists face as they attempt to continue the rate of progress to the identified terminus of the technology shrink path in about 2020. We could find at the electrical property as variation p base dose. Ultimately, its ON state voltage drop was enhanced also shrink chip size. To obtain an optimized parameter and design, we have simulated over 500 V Field ring using 8 Field rings. Field ring width was $3{\mu}m$ and P base dose was $1e15cm^2$. Also the numerical multiple $2.52cm^2$ was obtained which indicates the doping limit of the original device. We have simulated diffusion condition was split from $1,150^{\circ}C$ to $1,200^{\circ}C$. And then $1,150^{\circ}C$ diffusion time was best condition for break down voltage.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07a
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• pp.358-361
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• 2002

Self-aligned MOSFETS using a polysilicon gate are widely fabricated in silicon technology. The polysilicon layer acts as a mask for the source and drain implants and does as gate electrode in the final product. However, the usage of polysilicon gate as a self-aligned mask is restricted in fabricating SiC MOSFETS since the following processes such as dopant activation, ohmic contacts are done at the very high temperature to attack the stability of the polysilicon layer. A metal instead of polysilicon can be used as a gate material and even can be used for ohmic contact to source region of SiC MOSFETS, which may reduce the number of the fabrication processes. Co-formation process of metal-source/drain ohmic contact and gate has been examined in the 4H-SiC based vertical power MOSFET At low bias region (<20V), increment of leakage current after RTA was detected. However, the amount of leakage current increment was less than a few tens of ph. The interface trap densities calculated from high-low frequency C-V curves do not show any difference between w/ RTA and w/o RTA. From the C-V characteristic curves, equivalent oxide thickness was calculated. The calculated thickness was 55 and 62nm for w/o RTA and w/ RTA, respectively. During the annealing, oxidation and silicidation of Ni can be occurred. Even though refractory nature of Ni, 950$^{\circ}C$ is high enough to oxidize it. Ni reacts with silicon and oxygen from SiO$_2$ 1ayer and form Ni-silicide and Ni-oxide, respectively. These extra layers result in the change of capacitance of whole oxide layer and the leakage current

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.17 no.3
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• pp.259-266
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• 2004

In this paper. a new two types of EST(Emitter Switched Thyristor) structures are proposed to improve the electrical characteristics including the current saturation capability. Besides, the two dimensional numerical simulations were carried out using MEDICI to verify the validity of the device and examine the electrical characteristics. First, a vortical trench electrode EST device is proposed to improve snap-back effect and its blocking voltage. Second, a dual trench gate EST device is proposed to obtain high voltage current saturation characteristics and high blocking voltage and to eliminate snap-back effect. The two proposed devices have superior electrical characteristics when compared to conventional devices. In the vertical trench electrode EST, the snap-back effect is considerably improved by using the vertical trench gate and cathode electrode and the blocking voltage is one times better than that of the conventional EST. And in the dual trench gate EST, the snap-back effect is completely removed by using the series turn-on and turn-off MOSFET and the blocking voltage is one times better than that of the conventional EST. Especially current saturation capability is three times better than that of the other EST.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.7
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• pp.1-6
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• 2002

For an optimum device design of nano-scale SOI devices, this paper describes the short channel effects of multi-gate structures SOI MOSFETs such as double gate, triple gate and quadruple gate, as well as a new proposed Pi gate using computer simulation. The simulation has been performed with different channel doping concentrations, channel widths, silicon film thickness, and vertical gate extension depths of Pi gate. From the simulation results, it is found that Pi gate devices have a large margin in determination of doping concentrations, channel widths and film thickness comparing to double and triple gate devices because Pi gate devices offer a better short channel effects.

• Proceedings of the KIEE Conference
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• 2008.10b
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• pp.165-168
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• 2008

The experimental results of exposing IGBT (Insulated Gate Bipolar Transistor) samples to gamma radiation source show shifting of threshold voltages in the MOSFET and degradation of carrier mobility and current gains. At low total dose rate, the shift of threshold voltage is the major contribution of current increases, but for more than some total dose, the current is increased because of the current gain degradation occurred in the vertical PNP at the output of the IGBTs. In the paper, the collector current characteristics as a function of gate emitter voltage (VGE) curves are tested and analyzed with the model considering the radiation damage on the devices for gate bias and different dose. In addition, the model parameters between simulations and experiments are found and studied.

• Proceedings of the KIEE Conference
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• 2001.07c
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• pp.1424-1426
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• 2001

본 논문에서는 채널과 드리프트 영역을 트랜치 안쪽에 형성하여 소자 크기를 줄임으로서 항복전압을 감소시키지 않고 낮은 온 저항을 얻을 수 있는 새로운 수직방향 채널 LDMOS(Lateral Double Diffused MOSFET)를 제안한다. 기존의 LDMOS 구조와 비교 할 때 동일한 60V의 항복 전압에서 소자 크기가 4${\mu}m$로 줄어들었고 이에 따라 온 저항은 절반의 수준으로 (0.45 m${\Omega}cm^2$) 감소하였다. 또한 소자 크기의 감소로 인해 전력용 집적회로를 구성할 때 집적도가 두 배 가량 증가하게 된다.

• Journal of Sensor Science and Technology
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• v.23 no.4
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• pp.284-289
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• 2014

In this paper, modeling of a gate/body-tied (GBT) PMOSFET photodetector with built-in transfer gate is performed. It can control the photocurrent with a high-sensitivity. The GBT photodetector is a hybrid device consisted of a MOSFET, a lateral BJT, and a vertical BJT. This device allows for amplifying the photocurrent gain by $10^3$ due to the GBT structure. However, the operating parameters of this photodetector, including its photocurrent and transfer characteristics, were not known because modeling has not yet been performed. The sophisticated model of GBT photodetector using a process simulator is not compatible with circuit simulator. For this reason, we have performed SPICE modeling of the photodetector with reduced complexity using Cadence's Spectre program. The proposed modeling has been demonstrated by measuring fabricated chip by using 0.35 im 2-poly 4-metal standard CMOS technology.

• Journal of Sensor Science and Technology
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• v.24 no.5
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• pp.353-357
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• 2015

A new SPICE-compatible model for a gate/body-tied PMOSFET photodetector (GBT PD) with an overlapping control gate is presented. The proposed SPICE-compatible model of a GBT PD with an overlapping control gate makes it possible to control the photocurrent. Research into GBT PD modeling was proposed previously. However, the analysis and simulation of GBT PDs is not lacking. This SPICE model concurs with the measurement results, and it is simpler than previous models. The general GBT PD model is a hybrid device composed of a MOSFET, a lateral bipolar junction transistor (BJT), and a vertical BJT. Conventional SPICE models are based on complete depletion approximation, which is more applicable to reverse-biased p-n junctions; therefore, they are not appropriate for simulating circuits that are implemented with a GBT PD with an overlapping control gate. The GBT PD with an overlapping control gate can control the sensitivity of the photodetector. The proposed sensor is fabricated using a $0.35{\mu}m$ two-poly, four-metal standard complementary MOS (CMOS) process, and its characteristics are evaluated.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.406-406
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• 2010

일반적으로, 나노스케일의 MOS 소자에서는 게이트 절연체 두께가 감소함에 따라 tunneling effect의 증가로 인해 PID (plasma induced damage)로 인한 소자 특성 저하 현상을 감소하는 추세로 알려져 있다. 하지만 요즘 많이 사용되고 있는 high-k 게이트 절연체의 경우에는 오히려 더 많은 charge들이 trapping 되면서 PID가 오히려 더 심각해지는 현상이 나타나고 있다. 이러한 high-k 게이트 식각 시 현재는 주로 Hf-based wet etch나 dry etch가 사용되고 있지만 gate edge 영역에서 high-k 게이트 절연체의 undercut 현상이나 PID에 의한 소자특성 저하가 보고되고 있다. 본 연구에서는 이에 차세대 MOS 소자의 gate stack 구조중 issue화 되고 있는 metal gate 층과 gate dielectric 층의 식각공정에 각각 중성빔 식각과 중성빔 원자층 식각을 적용하여 전기적 손상 없이 원자레벨의 정확한 식각 조절을 해줄 수 있는 새로운 two step 식각 공정에 대한 연구를 진행하였다. 먼저 TiN metal gate 층의 식각을 위해 HBr과 $Cl_2$ 혼합가스를 사용한 중성빔 식각기술을 적용하여 100 eV 이하의 에너지 조건에서 하부층인 $HfO_2$와 거의 무한대의 식각 선택비를 얻었다. 하지만 100 eV 조건에서는 낮은 에너지에 의한 빔 스케터링으로 실제 패턴 식각시 etch foot이 발생되는 현상이 관찰되었으며, 이를 해결하기 위하여 먼저 높은 에너지로 식각을 진행하고 $HfO_2$와의 계면 근처에서 100 eV로 식각을 해주는 two step 방법을 사용하였다. 그 결과 anistropic 하고 하부층에 etch stop된 식각 형상을 관찰할 수 있었다. 다음으로 3.5nm의 매우 얇은 $HfO_2$ gate dielectric 층의 정확한 식각 깊이 조절을 위해 $BCl_3$와 Ar 가스를 이용한 중성빔 원자층 식각기술을 적용하여 $1.2\;{\AA}$/cycle의 단일막 식각 조건을 확립하고 약 30 cycle 공정시 3.5nm 두께의 $HfO_2$ 층이 완벽히 제거됨을 관찰할 수 있었다. 뿐만 아니라, vertical 한 식각 형상 및 향상된 표면 roughness를 transmission electron microscope(TEM)과 atomic force microscope (AFM)으로 관찰할 수 있었다. 이러한 중성빔 식각과 중성빔 원자층 식각기술이 결합된 새로운 gate recess 공정을 실제 MOSFET 소자에 적용하여 기존 식각 방법으로 제작된 소자 결과를 비교해 본 결과 gate leakage current가 약 one order 정도 개선되었음을 확인할 수 있었다.