• Journal of Information Management
• /
• v.42 no.3
• /
• pp.1-26
• /
• 2011

The domain of LED is analyzed for describing the current status of Korea's R&D in the domain comparing with those of others quantitatively. Fourteen sub-domains of LED manufacturing technology are selected and the time span for analysis is ten-year: 2001-2010. Bibiliometric analysis is performed by the unit of publication, core researcher, institution and country. Strategical diagram is also produced with devised two indicators: NGI and NPI. As a result, Korea is competitive in the area of Chip Scale Package, but R&D supports in another promising areas, such as large-caliber sapphire wafer, are necessary. It is also revealed that research activities are expanded dominantly in academia, but practical technologies are developed in industrial circle. It is suggested that to support core corporate and to encourage industrial-academic collaboration is essential for systematical technology development and high achievement in prominent areas.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.42 no.5 s.335
• /
• pp.15-22
• /
• 2005

This paper proposes an efficient structure which is able to perform self-detection and self-repair for faults in a digital system by imitating the structure of living beings. The self-repair system is composed of artificial cells, which have homogeneous structures in the two-dimension, and spare cells. An artificial cell is composed of a logic block based on multiplexers, and a genome block, which controls the logic block. The cell is designed using DCVSL (differential cascode voltage switch logic) structure to self-detect faults. If a fault occurs in an artificial cell, it is self-detected by the DCVSL. Then the artificial cells which belong to the column are disabled and reconfigured using both neighbour cells and spare cells to be repaired. A self-repairable 2-bit up/down counter has been fabricated using Hynix $0.35{\mu}m$ technology with $1.14{\times}0.99mm^2$ core area and verified through the circuit simulation and chip test.

• Journal of the Korean Society for Precision Engineering
• /
• v.17 no.4
• /
• pp.7-21
• /
• 2000

This paper describes an overview of the thixoforming and thixomolding processes. Semi-solid metalworking (SSM), which is called the thixoforming process of aluminium materials, incorporates the elements of both casting and for the manufacture of near net shape parts. The SSM has some advantages such as net shape or near net shape manufacturing, the ability to form thin walls, excellent surface finish, tight tolerance, and excellent dimensional precision. The thixomolding process of Mg alloy (AZ9l) is a combination of two technologies both conventional die casting and plastic injection molding. The feed material used is a machined chip with a geometry of approximately 1 mm square and a length of 2~3 mm. The semi-solid forming (SSF) of high quality aluminium and magnesium parts will be established in the automotive and electronic industry, in the future. The hybrid method of casting/forging has been caused attention. This process uses a preformed material made by casting instead of the wrought material and finishes it by a single forging process. This process is expected to lower costs without sacrificing the mechanical and finishes it by a single forging process. The process is expected to lower costs without sacrificing the mechanical properties. The authors, intending that the casting/forging process contributes to a reduction in production cost of aluminum automotive parts in Korea, describes the feature of the casting/forging process, aluminum alloys suitable for the cast preform, microstructure and mechanical properties of the cast preform, application examples of cast/forging, and further study.

• The Journal of the Korea Contents Association
• /
• v.13 no.10
• /
• pp.54-61
• /
• 2013

This paper presents a simplified hardware based edge detection circuit which is based on an analog correlator combining with the neighbor pixels in CMOS image sensor. A pixel element of the edge detector consists of an active pixel sensor and an analog correlator circuit which connects two neighbor pixels. The edge detector shares a comparator on each column that the comparator decides an edge of the target pixel with an adjustable reference voltage. The circuit detects image edge from CIS directly that reduces area and power consumption 4 times and 20%, respectively, compared with the previous works. And also it has advantage to regulate sensitivity of the edge detection because the threshold value is able to control externally. The fabricated chip has 34% of fill factor and 0.9 ${\mu}W$ of power per a pixel under 0.18 ${\mu}m$ CMOS technology.

• Asian-Australasian Journal of Animal Sciences
• /
• v.22 no.8
• /
• pp.1091-1101
• /
• 2009

In an attempt to understand the biochemical mechanism for the synthesis of the anabolic steroid, 19-nortestosterone, produced by prepubertal boar testes and its physiological role, normalized complementary DNA (cDNA) from boar testes was generated. DNA sequencing of 2,016 randomly selected clones yielded 794,116 base pairs of high quality nucleotide sequence. Computer-assisted assembly of the nucleotide sequence of each clone resulted in 423 contigs and 403 singletons including several genes for steroidogenic enzymes and molecules related to steroid metabolism. Analysis of gene expression pattern by use of the presently-fabricated cDNA microarray identified a number of genes that were differentially expressed during the postnatal development period in boar testes. Two genes of unknown function were identified to be highly expressed in the testis of 2-weeks-old neonatal boar. In addition, the sequencing of open reading frames of these genes revealed their homology with human alpha hemoglobin and Homo sapiens hypothetical LOC643669, transcript variant 1. Moreover, the transcripts of these genes were also detected in porcine muscle and adipocytes, in addition to Leydig cells of pigs.

• Journal of Korea Multimedia Society
• /
• v.13 no.7
• /
• pp.943-949
• /
• 2010

This paper presents some improvements on VLSI implementation of lifting-based 9/7 wavelet transform by optimization hardware multiplication. The proposed solution requires less logic area and power consumption without performance loss compared to previous wavelet filter structure based on lifting scheme. This paper proposes a better approach to the hardware implementation using Lefevre algorithm based on extensions of Pattern search methods. To compare the proposed structure to the previous solutions on full multiplier blocks, we implemented them using Verilog HDL. For a hardware implementation of the two solutions, the logical synthesis on 0.18 um standard cells technology show that area, maximum delay and power consumption of the proposed architecture can be reduced up to 51%, 43% and 30%, respectively, compared to previous solutions for a 200 MHz target clock frequency. Our evaluation show that when design VLSI chip of lifting-based 9/7 wavelet filter, our solution is better suited for standard-cell application-specific integrated circuits than prior works on complete multiplier blocks.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.44 no.1
• /
• pp.28-35
• /
• 2007

In this paper, an ultra low voltage SRAM design method based on dual-boosted cell bias technique is described. For each read/write cycle, the wordline and cell power node of the selected SRAM cells are boosted into two different voltage levels. This enhances SNM(Static Noise Margin) to a sufficient amount without an increase of the cell size, even at sub 1-V supply voltage. It also improves the SRAM circuit speed owing to increase of the cell read-out current. The proposed design technique has been demonstrated through 0.8-V, 32K-byte SRAM macro design in a $0.18-{\mu}m$ CMOS technology. Compared to the conventional cell bias technique, the simulation confirms an 135 % enhancement of the cell SNM and a 31 % faster speed at 0.8-V supply voltage. This prototype chip shows an access time of 23 ns and a power dissipation of $125\;{\mu}W/Hz$.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.11
• /
• pp.84-91
• /
• 2009

A high speed serial link transmitter using multi-level signaling is proposed. To achieve high data rate m high speed serial link, 4-pulse amplitude modulation (PAM) is used. By transmitting 2 bit data in each symbol time, high speed data transmission, two times than binary signaling, is achieved. The transmitter transmits current-mode output instead of voltage-mode output Current-mode output is much faster than voltage-mode output, so higher data transmission is available by increasing switching speed of driver. $2^5-1$ pseudo-random bit sequence (PRBS) generator is contained to perform built-in self test (BIST). The 4-PAM transmitter is designed in Dongbu HiTek $0.18{\mu}m$ CMOS technology and achieves 8 Gb/s, 160 mV of eye height with 1.8 V supply voltage. The transmitter consumes only 98 mW for 8 Gb/s transmission.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.16 no.1
• /
• pp.70-79
• /
• 2016

This paper proposes a low-power range-scaled 14b 30 MS/s pipeline-SAR composite ADC for high-performance CIS applications. The SAR ADC is employed in the first stage to alleviate a sampling-time mismatch as observed in the conventional SHA-free architecture. A range-scaling technique processes a wide input range of 3.0VP-P without thick-gate-oxide transistors under a 1.8 V supply voltage. The first- and second-stage MDACs share a single amplifier to reduce power consumption and chip area. Moreover, two separate reference voltage drivers for the first-stage SAR ADC and the remaining pipeline stages reduce a reference voltage disturbance caused by the high-speed switching noise from the SAR ADC. The measured DNL and INL of the prototype ADC in a $0.18{\mu}m$ CMOS are within 0.88 LSB and 3.28 LSB, respectively. The ADC shows a maximum SNDR of 65.4 dB and SFDR of 78.9 dB at 30 MS/s, respectively. The ADC with an active die area of $1.43mm^2$ consumes 20.5 mW at a 1.8 V supply voltage and 30 MS/s, which corresponds to a figure-of-merit (FOM) of 0.45 pJ/conversion-step.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.36C no.1
• /
• pp.49-58
• /
• 1999

This paper describes an integrated low pass filter fabricated by using $0.8{\mu}m$ single poly CMOS ASIC technology. The filter has been designed for a 5th-order elliptic switched capacitor filter with cutoff frequency of 5khz, 0.1dB passband ripple. The filter consists of MOS swiches poly capacitors and five CMOS op-amps. For the realization of the SC filter, continuous time transfer function H(s) is obtained from LC passive type, and transfered as discrete time transfer H(z) through bilinear-z transform. Another filter has been designed by capacitor scaling for reduced chip area, considering dynamic range of the op-amp. The test results of two fabricated filters are cutoff frequency of 4.96~4.98khz, 35~38dB gain attenuation and 0.72~0.81dB passband ripple with the ${\pm}2.5V$power supply clock of 50KHz.