• 한국진공학회:학술대회논문집
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• 한국진공학회 2011년도 제40회 동계학술대회 초록집
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• pp.167-167
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• 2011

Magnetic random access memory (MRAM) is one of the prospective semiconductor memories for next generation. It has the excellent features including nonvolatility, fast access time, unlimited read/write endurance, low operating voltage, and high storage density. MRAM consists of magnetic tunnel junction (MTJ) stack and complementary metal-oxide semiconductor (CMOS). The MTJ stack is composed of various magnetic materials, metals, and a tunneling barrier layer. For the successful realization of high density MRAM, the etching process of magnetic materials should be developed. Among various magnetic materials, FePt has been used for pinned layer of MTJ stack. The previous etch study of FePt magnetic thin films was carried out using $CH_4/O_2/NH_3$. It reported only the etch characteristics with respect to the variation of RF bias powers. In this study, the etch characteristics of FePt thin films have been investigated using an inductively coupled plasma reactive ion etcher in various etch chemistries containing $CH_4$/Ar and $CH_4/O_2/Ar$ gas mixes. TiN thin film was employed as a hard mask. FePt thin films are etched by varying the gas concentration. The etch characteristics have been investigated in terms of etch rate, etch selectivity and etch profile. Furthermore, x-ray photoelectron spectroscopy is applied to elucidate the etch mechanism of FePt thin films in $CH_4$/Ar and $CH_4/O_2/Ar$ chemistries.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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• pp.168-168
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• 2008

Dimension of a transistor has rapidly shrunk to increase the speed of device and to reduce the power consumption. However, it is accompanied with several problems like direct tunneling through the gate dioxide layer and low conductivity characteristic of poly-Si gate in nano-region. To cover these faults, study of new materials is urgently needed. Recently, high dielectric materials like $Al_2O_3$, $ZrO_2$, and $HfO_2$ are being studied for equivalent oxide thickness (EOT). However, poly-Si gate is not compatible with high-k materials for gate-insulator. Poly Si gate with high-k material has some problems such as gate depletion and dopant penetration problems. Therefore, new gate structure or materials that are compatible with high-k materials are also needed. TiN for metal/high-k gate stack is conductive enough to allow a good electrical connection and compatible with high-k materials. According to this trend, the study on dry etching of TiN for metal/high-k gate stack is needed. In this study, the investigations of the TiN etching characteristics were carried out using the inductively coupled $BCl_3$-based plasma system and adding $Cl_2$ gas. Dry etching of the TiN was studied by varying the etching parameters including $BCl_3$/Ar gas mixing ratio, RF power, DC-bias voltage to substrate, and $Cl_2$ gas addition. The plasmas were characterized by optical emission spectroscopy analysis. Scanning electron microscopy was used to investigate the etching profile.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 하계학술대회 논문집 Vol.8
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• pp.20-20
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• 2007

Nanowire-based field-effect transistors (FETs) decorated with nanoparticles have been greatly paid attention as nonvolatile memory devices of next generation due to their excellent transportation ability of charge carriers in the channel and outstanding capability of charge trapping in the floating gate. In this work, top-gate single ZnO nanowire-based FETs with and without Au nanoparticles were fabricated and their memory effects were characterized. Using thermal evaporation and rapid thermal annealing processes, Au nanoparticles were formed on an $Al_2O_3$ layer which was semi cylindrically coated on a single ZnO nanowire. The family of $I_{DS}-V_{GS}$ curves for the double sweep of the gate voltage at $V_{DS}$ = 1 V was obtained. The device decorated with nanoparticles shows giant hysterisis loops with ${\Delta}V_{th}$ = 2 V, indicating a significant charge storage effect. Note that the hysterisis loops are clockwise which result from the tunneling of the charge carriers from the nanowire into the nanoparticles. On the other hand, the device without nanoparticles shows a negligible countclockwise hysterisis loop which reveals that the influence of oxide trap charges or mobile ions is negligible. Therefore, the charge storage effect mainly comes from the nanoparticles decorated on the nanowire, which obviously demonstrates that the top-gate single ZnO nanowire-based FETs decorated with Au nanoparticles are the good candidate for the application in the nonvolatile memory devices of next generation.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2009년도 제38회 동계학술대회 초록집
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• pp.381-381
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• 2010

$(ZrO_2)_{0.66}(HfO_2)_{0.34}$ thin films as gate dielectrics have been proposed to overcome the problems of tunneling current and degradation mobility inachieving a thin equivalent oxide thickness. An extremely thin $SiO_2$ layer is used in order to separate the carrier in MOSFET channel from the dielectric field fluctuation caused by phonons in the dielectric which decreases the carrier mobility. The electronic and optical properties influenced the device performance to a great extent. $(ZrO_2)_{0.66}(HfO_2)_{0.34}$ dielectric films on p-Si (100) were grown by atomic layer deposition method, for which the conduction band offsets, valence band offsets and band gapswere obtained by using X-ray photoelectron spectroscopy and reflection electron energy loss spectroscopy. The band gap, valence and conduction band offset values for $(ZrO_2)_{0.66}(HfO_2)_{0.34}$ dielectric thin film, grown on Si substrate were about 5.34, 2.35 and 1.87 eV respectively. This band alignment was similar to that of $ZrO_2$. In addition, The dielectric function (k, $\omega$), index of refraction n and the extinction coefficient k for the $(ZrO_2)_{0.66}(HfO_2)_{0.34}$ thin films were obtained from a quantitative analysis of REELS data by comparison to detailed dielectric response model calculations using the QUEELS-$\varepsilon$(k, $\omega$)-REELS software package. These optical properties are similar with $ZrO_2$ dielectric thin films.

• 한국전기전자재료학회논문지
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• 제36권2호
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• pp.125-128
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• 2023

Recently, as the process of the MOS device becomes more detailed, and the degree of integration thereof increases, many problems such as leakage current due to an increase in electron tunneling due to the thickness of SiO₂ used as a gate oxide have occurred. In order to overcome the limitation of SiO₂, many studies have been conducted on HfO₂ that has a thermodynamic stability with silicon during processing, has a higher dielectric constant than SiO₂, and has an appropriate band gap. In this study, HfO₂, which is attracting attention in various fields, was doped with Al and the change in properties according to its concentration was studied. Al-doped HfO₂ thin film was deposited using Plasma Enhanced Atomic Layer Deposition (PEALD), and the structural and electrical characteristics of the fabricated MIM device were evaluated. The results of this study are expected to make an essential cornerstone in the future field of next-generation semiconductor device materials.

• 한국진공학회지
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• 제16권6호
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• pp.453-457
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• 2007

상온에서 RF magnetron sputtering 을 이용하여 10nm에서 50nm 의 두께를 가지는 ZnO와 GZO 를 유리 기판위에 증착하여 두 물질 간의 구조적 특성과 광학적 특성을 평가하였다. 구조적인 특성은 투과전자현미경 (TEM) 과 주사전자현미경 (SEM)을 통해 이루어졌다. 광학적 특성 평가는 spectrophotometer를 이용하여 UV-VIS-NIR 영역에 관한 투과도를 측정하였다. ZnO의 결정크기가 GZO보다 상대적으로 더 크게나왔으며 이는 결정 경계면에서 발생하는 광산란을 줄임으로서 투과도의 향상을 가져왔다. 투과 전 영역에서 ZnO의 투과도가 더 높게 나왔으며, 특히 50nm 박막의 경우 ZnO의 투과도가 GZO 보다 20% 이상 더 뛰어난 것을 확인 할 수 있었다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2011년도 제40회 동계학술대회 초록집
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• pp.134-134
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• 2011

High-k dielectric materials such as $HfO_2$, $ZrO_2$ and $Al_2O_3$ increase gate capacitance and reduce gate leakage current in MOSFET structures. This behavior suggests that high-k materials will be promise candidates to substitute as a tunnel barrier. Furthermore, stack structure of low-k and high-k tunnel barrier named variable oxide thickness (VARIOT) is more efficient.[1] In this study, we fabricated the $WSi_2$ nanocrystals nonvolatile memory device with $SiO_2/HfO_2/Al_2O_3$ tunnel layer. The $WSi_2$ nano-floating gate capacitors were fabricated on p-type Si (100) wafers. After wafer cleaning, the phosphorus in-situ doped poly-Si layer with a thickness of 100 nm was deposited on isolated active region to confine source and drain. Then, on the gate region defined by using reactive ion etching, the barrier engineered multi-stack tunnel layers of $SiO_2/HfO_2/Al_2O_3$ (2 nm/1 nm/3 nm) were deposited the gate region on Si substrate by using atomic layer deposition. To fabricate $WSi_2$ nanocrystals, the ultrathin $WSi_2$ film with a thickness of 3-4 nm was deposited on the multi-stack tunnel layer by using direct current magnetron sputtering system [2]. Subsequently, the first post annealing process was carried out at $900^{\circ}C$ for 1 min by using rapid thermal annealing system in nitrogen gas ambient. The 15-nm-thick $SiO_2$ control layer was deposited by using ultra-high vacuum magnetron sputtering. For $SiO_2$ layer density, the second post annealing process was carried out at $900^{\circ}C$ for 30 seconds by using rapid thermal annealing system in nitrogen gas ambient. The aluminum gate electrodes of 200-nm thickness were formed by thermal evaporation. The electrical properties of devices were measured by using a HP 4156A precision semiconductor parameter analyzer with HP 41501A pulse generator, an Agillent 81104A 80MHz pulse/pattern generator and an Agillent E5250A low leakage switch mainframe. We will discuss the electrical properties for application next generation non-volatile memory device.

• 한국전기전자재료학회논문지
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• 제34권4호
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• pp.251-255
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• 2021

a-Si is commonly considered as a primary candidate for the formation of passivation layer in heterojunction (HIT) solar cells. However, there are some problems when using this material such as significant losses due to recombination and parasitic absorption. To reduce these problems, a wide bandgap material is needed. A wide bandgap has a positive influence on effective transmittance, reduction of the parasitic absorption, and prevention of unnecessary epitaxial growth. In this paper, the adoption of a-SiO_x:H as the intrinsic layer was discussed. To increase lifetime and conductivity, oxygen concentration control is crucial because it is correlated with the thickness, bonding defect, interface density (D_it), and band offset. A thick oxygen-rich layer causes the lifetime and the implied open-circuit voltage to drop. Furthermore the thicker the layer gets, the more free hydrogen atoms are etched in thin films, which worsens the passivation quality and the efficiency of solar cells. Previous studies revealed that the lifetime and the implied voltage decreased when the a-SiOx thickness went beyond around 9 nm. In addition to this, oxygen acted as a defect in the intrinsic layer. The D_it increased up to an oxygen rate on the order of 8%. Beyond 8%, the D_it was constant. By controlling the oxygen concentration properly and achieving a thin layer, high-efficiency HIT solar cells can be fabricated.

• 한국진공학회지
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• 제21권5호
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• pp.273-278
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• 2012

현재 Hf (Hafnium)을 기반으로한 게이트 유전체의 연구는 여러 분야에서 다양하게 진행되어져 왔다. 이는 기존의 $SiO_2$보다 유전상수 값이 크고, 또한 계속되는 scaling-down 공정에서도 양자역학적인 터널링을 차단하는 특성이 뛰어나기 때문이다. MOSFET 구조에서 유전체 박막의 두께 감소로 인한 전기적 특성 저하를 보완하기 위해서 high-K 재료가 대두되었고 현재 주를 이루고 있다. 그러나 현재까지 $HfO_2$에 대한 nano-mechanical 특성 연구는 부족한 상태이므로 본 연구에서는 게이트 절연층으로 최적화하기 위하여 $HfO_2$ 박막의 nano-mechanical properties를 자세히 조사하였다. 시료는 rf magnetron sputter를 이용하여 Si (silicon) 기판 위에 Hafnium target으로 산소유량(4, 8 sccm)을 달리하여 증착하였고, 이후 furnace에서 400에서 $800^{\circ}C$까지 질소분위기에서 20분간 열처리를 실시하였다. 실험결과 산소 유량을 8 sccm으로 증착한 시료가 열처리 온도가 증가할수록 누설전류 특성 성능이 우수 해졌다. Nano-indenter로 측정하고 Weibull distribution으로 정량적 계산을 한 결과, $HfO_2$ 박막의 stress는 as-deposited 시료를 기준으로 $400^{\circ}C$에서는 tensile stress로 변화되었다. 그러나 온도가 증가(600, $800^{\circ}C$)할수록 compressive stress로 변화 되었다. 특히, $400^{\circ}C$ 열처리한 시료에서 hardness 값이 (산소유량 4 sccm : 5.35 GPa, 8 sccm : 5.54 GPa) 가장 감소되었다. 반면에 $800^{\circ}C$ 열처리한 시료에서는(산소유량 4 sccm : 8.09 GPa, 8 sccm : 8.17 GPa) 크게 증가된 것을 확인하였다. 이를 통해 온도에 따른 $HfO_2$ 박막의 stress 변화를 해석하였다.