• 대한전기학회:학술대회논문집
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• 대한전기학회 1993년도 하계학술대회 논문집 B
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• pp.1265-1267
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• 1993

The switching and the retention characteristics with the injection conditions(pulse height and pulse width) were investigated in the nonvolatile MNOS memories with thin oxide layer of $23{\AA}$ thick. The shift of flatband voltage was measured using the fast ramp C-V method and experimental results were analized using the previously developed models. It was shown that the experimental results were described quit well by the trap-assisted and modified Fowler-Nordheim tunneling models for the voltage pulse of $15V{\sim}19V,\;24V{\sim}25V$, respectively. However, the direct tunneling model was agreement with experimental values in all range of pulse height. As increasing the initial shift of the flatband voltage, the decay rate was increased. But for the same initial shift of the flatband voltage, the decay rate was smaller for low and long pulse than for high and short one.

• 한국정보통신학회논문지
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• 제21권6호
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• pp.1069-1074
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• 2017

항복전압의 감소는 채널길이 감소에 의하여 발생하는 심각한 단채널 효과이다. 본 논문에서는 10 nm 이하 채널길이를 갖는 이중게이트 MOSFET에서 채널크기의 변화를 파라미터로 하여 채널도핑에 따른 항복전압의 변화를 고찰하였다. 이를 위하여 해석학적 전위분포에 의한 열방사 전류와 터널링 전류를 구하고 두 성분의 합으로 구성된 드레인 전류가 $10{\mu}A$가 될 때, 드레인 전압을 항복전압으로 정의하였다. 결과적으로 채널 도핑농도가 증가할수록 항복전압은 크게 증가하였다. 채널길이가 감소하면서 항복전압이 크게 감소하였으며 이를 해결하기 위하여 실리콘 두께 및 산화막 두께를 매우 작게 유지하여야만 한다는 것을 알 수 있었다. 특히 터널링 전류의 구성비가 증가할수록 항복전압이 증가하는 것을 관찰하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제8권1호
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• pp.27-31
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• 2008

We have studied nonvolatile memory properties of MOSFETs with double-stacked Si nanoclusters in the oxide-gate stacks. We formed Si nanoclusters of a uniform size distribution on a 5 nm-thick tunneling oxide layer, followed by a 10 nm-thick intermediate oxide and a second layer of Si nanoclusters by using LPCVD system. We then investigated the memory characteristics of the MOSFET and observed that the charge retention time of a double-stacked Si nanocluster MOSFET was longer than that of a single-layer device. We also found that the double-stacked Si nanocluster MOSFET is suitable for use as a dual-bit memory.

• JSTS:Journal of Semiconductor Technology and Science
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• 제4권2호
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• pp.94-99
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• 2004

silicided 50-nm-gate-length n-type Schottky barrier metal-oxide-semiconductor field-effect-transistors (SB-MOSFETs) with 5 nm gate oxide thickness are manufactured. The saturation current is $120{\mu}A/{\mu}m$ and on/off-current ratio is higher than $10^5$ with low leakage current less than $10{\mu}A/{\mu}m$. Novel phenomena of this device are discussed. The increase of tunneling current with the increase of drain voltage is explained using drain induced Schottky barrier thickness thinning effect. The abnormal increase of drain current with the decrease of gate voltage is explained by hole carrier injection from drain into channel. The mechanism of threshold voltage increase in SB-MOSFETs is discussed. Based on the extracted model parameters, the performance of 10-nm-gate-length SB-MOSFETs is predicted. The results show that the subthreshold swing value can be lower than 60 mV/decade.

• Journal of Magnetics
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• 제10권4호
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• pp.137-141
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• 2005

We confirmed that the improvement in properties of magnetic tunnel junctions prepared by radical oxidation after thermal treatment was mostly resulted from the redistribution of oxygen at the $AIOx/Co_{90}Fe_{10}$ interface. The as-deposited Al oxide barrier was oxygen-deficient but most of it re-oxidized into $Al_2O_3$, the thermodynamically stable stoichiometric phase, through thermal treatment. As a result, the effective barrier height was increased from 1.52 eV to 2.27 eV. On the other hand, the effective barrier width was decreased from 8.2 ${\AA}$ to 7.5 ${\AA}$. X-ray absorption spectra of Fe and Co clearly showed that the oxygen in the CoFe layer diffused back into the Al barrier and thereby enriched the barrier to close to a stoichiometirc $Al_2O_3$ phase. The oxygen bonded with Co and Fe diffused back by 6.8 ${\AA}$ and 4.5 ${\AA}$ after thermal treatment, respectively. Our results confirm that controlling the chemical structures of the interface is important to improve the properties of magnetic tunnel junctions.

• E2M - 전기 전자와 첨단 소재
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• 제7권3호
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• pp.231-235
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• 1994

The multi-dielectric layer $SiO_2$/$Si_3{N_4}$/$SiO_2$ (ONO) is used to improve charge retention and to scale down the memory device. The nitride layer of MNOS device is oxidize to form ONO system. During the oxidation of the nitride layer, the change of thickness of nitride layer and generation of interface state between nitride layer and top oxide layer occur. In this paper, effects of oxidation of the nitride layer is studied. The decreases of the nitride layer due to oxidation and trapping characteristics of interface state of multi layer dielectric film are investigated through the C-V measurement and F-N tunneling injection experiment using SONOS capacitor structure. Based on the experimental results, carrier trapping model for maximum flatband voltage shift of multi layer dielectric film is proposed and compared with experimental data. As a results of curve fitting, interface trap density between the top oxide and layer is determined as being $5{\times}10^11$~$2{\times}10^12$[$eV^1$$cm^2$].

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2003년도 추계학술대회 논문집 Vol.16
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• pp.435-438
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• 2003

The effects of oxygen partial pressure and vacuum annealing on the electrical properties of sputtered vanadium oxide($VO_x$) thin films were investigated. The thin films were prepared by r.f. magnetron sputtering from $V_2O_5$ target in a gas mixture of argon and oxygen. The oxygen/(oxygen+argon) partial pressure ratio of 0% and 8% is adopted. Electrical properties of films sputter-deposited under different oxygen gas pressures and in situ annealed in vacuum at $400^{\circ}C$ for 1h and 4h are characterized through electrical conductivity measurements. I-V characteristics were distinguished between linear and nonlinear region. In the low field region the conduction is due to Schottky emission, while at high fields it changes to Fowler-Nordheim tunneling type conduction. The conductivity measurements have shown an Arrhenius dependence of the conductivity on the temperature.

• 한국재료학회지
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• 제30권7호
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• pp.333-337
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• 2020

Orthorhombic DyMnO₃ films are fabricated epitaxially on Nb-1.0 wt%-doped SrTiO₃ single crystal substrates using pulsed laser deposition technique. The structure of the deposited DyMnO₃ films is studied by X-ray diffraction, and the epitaxial relationship between the film and the substrate is determined. The electrical transport properties reveal the diodelike rectifying behaviors in the all-perovskite oxide junctions over a wide temperature range (100 ~ 340 K). The forward current is exponentially related to the forward bias voltage, and the extracted ideality factors show distinct transport mechanisms in high and low positive regions. The leakage current increases with increasing reverse bias voltage, and the breakdown voltage decreases with decrease temperature, a consequence of tunneling effects because the leakage current at low temperature is larger than that at high temperature. The determined built-in potentials are 0.37 V in the low bias region, and 0.11 V in the high bias region, respectively. The results show the importance of temperature and applied bias in determining the electrical transport characteristics of all-perovskite oxide heterostructures.

• 대한전자공학회논문지SD
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• 제41권11호
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• pp.7-13
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• 2004

두께가 약 3 nm 인 게이트 산화막을 갖는 P 및 NMOSFET를 제조하여 높은 압력 (5 atm.)의 중수소 및 수소 분위기에서 후속 열처리를 각각 행하여 중수소 효과(동위원소 효과)를 관찰하였다. 소자에 대한 스트레스는 -2.5V ≤ V/sub g/ ≤-4.0V 범위에서 100℃의 온도를 유지하며 진행되었다. 낮은 스트레스 전압에서는 실리콘 계면에 존재하는 정공에 의하여 게이트 산화막의 열화가 진행되었다. 그러나 스트레스 전압을 증가시킴으로써 높은 에너지를 갖는 전자에 의한 계면 결함 생성이 열화의 직접적인 원인이 됨을 알 수 있었다. 본 실험조건에서는 실리콘 계면에서 phonon 산란이 많이 발생하여 impact ionization에 의한 "hot" 정공의 생성은 무시할 수 있었다. 중수소 열처리를 행함으로써 수소 열처리에 비해 소자의 파라미터 변화가 적었으며, 게이트 산화막의 누설전류도 억제됨이 확인되었다. 이러한 결과로부터 impact ionization이 발생되지 않을 정도의 낮은 스트레스 전압동안 발생하는 게이트 산화막내 결함 생성은 수소 결합과 직접적인 관계가 있음을 확인하였다.

• 한국진공학회지
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• 제18권4호
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• pp.302-309
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• 2009

쇼트키 장벽 관통 트랜지스터에 실리콘 나노점을 부유 게이트로 사용하는 비휘발성 메모리 소자를 제작하였다. 소스/드레인 영역에 어븀 실리사이드를 형성하여 쇼트키 장벽을 생성하였으며, 디지털 가스 주입의 저압 화학 기상 증착법으로 실리콘 나노점을 형성하여 부유 게이트로 이용하였다. 쇼트키 장벽 관통 트랜지스터의 동작 상태를 확인하였으며, 게이트 전압의 크기 및 걸어준 시간에 따른 트랜지스터의 문턱전압의 이동을 관찰함으로써 비휘발성 메모리 특성을 측정하였다. 초기 ${\pm}20\;V$의 쓰기/지우기 동작에 따른 메모리 창의 크기는 ${\sim}5\;V$ 이었으며, 나노점에 충분한 전하 충전을 위한 동작 시간은 10/50 msec 이었다. 그러나 메모리 창의 크기는 일정 시간이 지난 후에 0.4 V로 감소하였다. 이러한 메모리 창의 감소 원인을 어븀 확산에 따른 결과로 설명하였다. 본 메모리 소자는 비교적 안정한 쓰기/지우기 내구성을 보여주었으나, 지속적인 쓰기/지우기 동작에 따라 수 V의 문턱전압 이동과 메모리 창의 감소를 보여주었다. 본 실험 결과를 가지고 실리콘 나노점 부유게이트가 쇼트키 장벽 트랜지스터 구조에 접목 가능하여 초미세 비휘발성 메모리 소자로 개발 가능함을 확인하였다.