• Journal of the Korean Institute of Telematics and Electronics
• /
• v.23 no.1
• /
• pp.65-73
• /
• 1986

Experiment have been conducted about thin oxide characteristics according to O2/N2 ratio needed for EEPROM cell fabrication. As a result, we think that there is no problem even if we grow oxide layer with large O2/N2 ratio and short exidation time and when the water is implated by As before oxidation, the oxide breakdown field is about IMV/cm lower than that is not implanted. Especially, the thin oxide characteristic seems to be affected largely by wafer cleaning and oxidation in air. On the basis of these, tunnel type EEPROM cell is fabricated by 3um CMOS process and its characteristic is studied. Tunnel oxide thickness(100\ulcorner is chosen to allow Fowler-Nordheim tunneling to charge the floating gate at the desired programming voltage and tunnel area(2x2um\ulcorneris chosen to increase capacitive coupling ratio. For program operation, high voltage (20-22V) is applied to the control gate, while both drain and source are gdrounded. The drain voltage for erase is 16V. It is shown that charge retention characteristics is not limited by leakage in the oxide and program/erase endurance is over 10E4 cycles of program erase operation.

• Journal of Sensor Science and Technology
• /
• v.26 no.2
• /
• pp.79-84
• /
• 2017

The drain current of the SB MOSFET was analytically modeled by an equation composed of thermionic emission and tunneling with consideration of the image force lowering. The depletion region electron concentration was used to model the channel electron concentration for the tunneling current. The Schottky barrier width is dependent on the channel electron concentration. The drain current is changed by the gate oxide thickness and Schottky barrier height, but it is hardly changed by the doping concentration. For a GaN SB MOSFET with ITO source and drain electrodes, the calculated threshold voltage was 3.5 V which was similar to the measured value of 3.75 V and the calculated drain current was 1.2 times higher than the measured.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2011.02a
• /
• pp.318-318
• /
• 2011

Etching of an ultrathin aluminum oxide film on NiAl(110) substrate by methanol is studied by home-built scanning tunneling microscopy at room-temperature. We deposited liquid methanol on thin alumina film by using a high speed solenoid valve suitable for deposition of thermally unstable molecules. It is found that only the reflection domain boundary between two domains was preferentially etched by methanol. Since the reflection domain boundary has many oxygen vacancies and irregular structures, judging from the fact, we assume that oxygen vacancies cause the chemically reactive phenomena of methanol in reflection domain boundary on an alumina film. The reactivity of the reflection domain boundary is attributed to the oxygen vacancies due to irregular structures. Similar reactivity is found on the oxygen deficient alumina produced on top of the intact alumina.

• Proceeding of EDISON Challenge
• /
• 2015.03a
• /
• pp.357-364
• /
• 2015

In this work, we investigate the quantum effects exhibited from ultra-thin GAA(gate-all-around) Nanowire FETs for Sub 14nm Technology. We face designing challenges particularly short channel effects (SCE). However traditional MOSFET SCE models become invalid due to unexpected quantum effects. In this paper, we investigated various performance factors of the GAA Nanowire FET structure, which is promising future device. We observe a variety of quantum effects that are not seen when large scale. Such are source drain tunneling due to short channel lengths, drastic threshold voltage increase caused by quantum confinement for small channel area, leakage current through thin gate oxide by tunneling, induced source barrier lowering by fringing field from drain enhanced by high k dielectric, and lastly the I-V characteristic dependence on channel materials and transport orientations owing to quantum confinement and valley splitting. Understanding these quantum phenomena will guide to reducing SCEs for future sub 14nm devices.

• Journal of Magnetics
• /
• v.6 no.4
• /
• pp.126-128
• /
• 2001

The effect of rapid thermal anneal (RTA) has been investigated on the properties of an FeMn exchange-biased magnetic tunnel junction (MTJ) using magnetoresistance and I-V measurements and transmission electron microscopy (TEM). The tunneling magnetoresistance (TMR) in an as-grown MTJ is found to be ∼27%, while the TMR in MTJs annealed by RTA increases with annealing temperature up to 300$\^{C}$, reaching ∼46%. A TEM image reveals a structural change in the interface of A1$_2$O$_3$layer for the MTJ annealed by RTA at 300$\^{C}$. The oxide barrier parameters are found to vary abruptly with annealing time within a few ten seconds. Our results demonstrate that the present RTA enhances the magnetoresistive properties of MTJs.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.11 no.2
• /
• pp.80-87
• /
• 2011

Low temperature hole transport characteristics of gate-all-around p-channel metal oxide semiconductor (PMOS) type silicon nanowire field-effect-transistors with the radius of 5 nm and lengths of 44-46 nm are presented. They show coexisting two single hole states randomly switching between each other. Analysis of Coulomb diamonds of these two switching states reveals a variety of electrostatic effects which is originated by the potential of a single hole captured in the trap near the nanowire.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2006.06a
• /
• pp.412-413
• /
• 2006

The electrical conduction mechanism of ITO / Terbium tris - (1 - phenyl - 3 - methyl - 4 - (tertiarybutyryl) - pyrazol - 5 - one) triphenylphosphine oxide [$(tb-PMP)_3Tb-(Ph_3PO)$]/Mg/Al devices has been investigated. The calculation of electric field in single layer organic layer between cathode and anode shows the uniform distribution for the electron injection barrier of over 1.4 eV. The measured current-voltage curve shows well matching with the calculated curve based on the tunneling injection of electron under the uniform distribution of electric field.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2001.07a
• /
• pp.729-732
• /
• 2001

In this study, the effect of oxygen partial pressure on the electrical properties of vanadium oxide(VO$_{x}$) thin films were investigated. The thin films were prepared by r.f. magnetron sputtering from V$_2$O$_{5}$ target in a gas mixture of argon and oxygen. The oxygen partial pressure ratio is changed from 0% to 8%. I-V characteristics were distinguished between linear and nonlinear region. In the low field region the conduction is due to Schottky emission, while at high fields it changes to Fowler-Nordheim tunneling type conduction. The conductivity measurements have shown an Arrhenius dependence of the conductivity on the temperature.ure.

• Journal of Applied Reliability
• /
• v.10 no.1
• /
• pp.65-71
• /
• 2010

NAND-type SONOS with a separated double-gate FinFET structure (SDF-Fin SONOS) flash memory devices are proposed to reduce the unit cell size of the memory device and increase the memory density in comparison with conventional non volatile memory devices. The proposed memory device consists of a pair of control gates separated along the direction of the Fin width. There are two unique alternative technologies in this study. One is a channel doping method and the other is an oxide thickness variation method, which are used to operate the SDF-Fin SONOS memory device as two-bit. The fabrication processes and the device characteristics are simulated by using technology comuter-adided(TCAD). The simulation results indicate that the charge trap probability depends on the different channel doping concentration and the tunneling oxide thickness. The proposed SDG-Fin SONOS memory devices hold promise for potential application.

• Electrical & Electronic Materials
• /
• v.7 no.2
• /
• pp.123-129
• /
• 1994

SONOS EEPROM chips, containing several SONOSFET nonvolatile memories of various channel size, have been fabricated on the basis of the existing n-well CMOS processing technology for 1 Mbit DRAM ($1.2\mu\textrm{m}$.m design rule). All the SONOSFET memories have the triple insulated-gate consisting of 30.angs. tunneling oxide, 205.angs. nitride and 65.angs. blocking oxide. The miniaturization of the devices for the higher density EEPROM and their characteristics alterations accompanied with the scaling-down have been investigated. The stabler operating characteristics were attained by increasing the ratio of the channel width to length. Also, the transfer, switching, retention and degradation characteristics of the most favorable performance devices were presented and discussed.