• Title/Summary/Keyword: tunneling oxide

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A Study on the Retention Characteristics with the Charge Injection Conditions in the Nonvolatile MNOS Memories (전하주입조건에 따른 비휘발성 MNOS 기억소자의 기억유지특성에 관한 연구)

  • Lee, Kyoung-Leun;Yi, Sang-Bae;Lee, Sang-Eun;Seo, Kwang-Yell
    • Proceedings of the KIEE Conference
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    • 1993.07b
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    • pp.1265-1267
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    • 1993
  • The switching and the retention characteristics with the injection conditions(pulse height and pulse width) were investigated in the nonvolatile MNOS memories with thin oxide layer of $23{\AA}$ thick. The shift of flatband voltage was measured using the fast ramp C-V method and experimental results were analized using the previously developed models. It was shown that the experimental results were described quit well by the trap-assisted and modified Fowler-Nordheim tunneling models for the voltage pulse of $15V{\sim}19V,\;24V{\sim}25V$, respectively. However, the direct tunneling model was agreement with experimental values in all range of pulse height. As increasing the initial shift of the flatband voltage, the decay rate was increased. But for the same initial shift of the flatband voltage, the decay rate was smaller for low and long pulse than for high and short one.

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Relation of Breakdown Voltage and Channel Doping Concentration of Sub-10 nm Double Gate MOSFET (10 nm 이하 DGMOSFET의 항복전압과 채널도핑농도의 관계)

  • Jung, Hakkee
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.21 no.6
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    • pp.1069-1074
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    • 2017
  • Reduction of breakdown voltage is serious short channel effect (SCE) by shrink of channel length. The deviation of breakdown voltage for doping concentration is investigated with structural parameters of sub-10 nm double gate (DG) MOSFET in this paper. To analyze this, thermionic and tunneling current are derived from analytical potential distribution, and breakdown voltage is defined as drain voltage when the sum of two currents is $10{\mu}A$. As a result, breakdown voltage increases with increase of doping concentration. Breakdown voltage decreases by reduction of channel length. In order to solve this problem, it is found that silicon and oxide thicknesses should be kept very small. In particular, as contributions of tunneling current increases, breakdown voltage increases.

Nonvolatile Memory Characteristics of Double-Stacked Si Nanocluster Floating Gate Transistor

  • Kim, Eun-Kyeom;Kim, Kyong-Min;Son, Dae-Ho;Kim, Jeong-Ho;Lee, Kyung-Su;Won, Sung-Hwan;Sok, Jung-Hyun;Hong, Wan-Shick;Park, Kyoung-Wan
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.8 no.1
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    • pp.27-31
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    • 2008
  • We have studied nonvolatile memory properties of MOSFETs with double-stacked Si nanoclusters in the oxide-gate stacks. We formed Si nanoclusters of a uniform size distribution on a 5 nm-thick tunneling oxide layer, followed by a 10 nm-thick intermediate oxide and a second layer of Si nanoclusters by using LPCVD system. We then investigated the memory characteristics of the MOSFET and observed that the charge retention time of a double-stacked Si nanocluster MOSFET was longer than that of a single-layer device. We also found that the double-stacked Si nanocluster MOSFET is suitable for use as a dual-bit memory.

Novel properties of erbium-silicided n-type Schottky barrier metal-oxide-semiconductor field-effect-transistors

  • Jang, Moon-Gyu;Kim, Yark-Yeon;Shin, Jae-Heon;Lee, Seong-Jae;Park, Kyoung-Wan
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.4 no.2
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    • pp.94-99
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    • 2004
  • silicided 50-nm-gate-length n-type Schottky barrier metal-oxide-semiconductor field-effect-transistors (SB-MOSFETs) with 5 nm gate oxide thickness are manufactured. The saturation current is $120{\mu}A/{\mu}m$ and on/off-current ratio is higher than $10^5$ with low leakage current less than $10{\mu}A/{\mu}m$. Novel phenomena of this device are discussed. The increase of tunneling current with the increase of drain voltage is explained using drain induced Schottky barrier thickness thinning effect. The abnormal increase of drain current with the decrease of gate voltage is explained by hole carrier injection from drain into channel. The mechanism of threshold voltage increase in SB-MOSFETs is discussed. Based on the extracted model parameters, the performance of 10-nm-gate-length SB-MOSFETs is predicted. The results show that the subthreshold swing value can be lower than 60 mV/decade.

Effect of Thermal Treatment on AIOx/Co90Fe10 Interface of Magnetic Tunnel Junctions Prepared by Radical Oxidation

  • Lee, Don-Koun;In, Jang-Sik;Hong, Jong-Ill
    • Journal of Magnetics
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    • v.10 no.4
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    • pp.137-141
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    • 2005
  • We confirmed that the improvement in properties of magnetic tunnel junctions prepared by radical oxidation after thermal treatment was mostly resulted from the redistribution of oxygen at the $AIOx/Co_{90}Fe_{10}$ interface. The as-deposited Al oxide barrier was oxygen-deficient but most of it re-oxidized into $Al_2O_3$, the thermodynamically stable stoichiometric phase, through thermal treatment. As a result, the effective barrier height was increased from 1.52 eV to 2.27 eV. On the other hand, the effective barrier width was decreased from 8.2 ${\AA}$ to 7.5 ${\AA}$. X-ray absorption spectra of Fe and Co clearly showed that the oxygen in the CoFe layer diffused back into the Al barrier and thereby enriched the barrier to close to a stoichiometirc $Al_2O_3$ phase. The oxygen bonded with Co and Fe diffused back by 6.8 ${\AA}$ and 4.5 ${\AA}$ after thermal treatment, respectively. Our results confirm that controlling the chemical structures of the interface is important to improve the properties of magnetic tunnel junctions.

The oxidation of silicon nitride layer (실리콘 질화막의 산화)

  • 정양희;이영선;박영걸
    • Electrical & Electronic Materials
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    • v.7 no.3
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    • pp.231-235
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    • 1994
  • The multi-dielectric layer $SiO_2$/$Si_3{N_4}$/$SiO_2$ (ONO) is used to improve charge retention and to scale down the memory device. The nitride layer of MNOS device is oxidize to form ONO system. During the oxidation of the nitride layer, the change of thickness of nitride layer and generation of interface state between nitride layer and top oxide layer occur. In this paper, effects of oxidation of the nitride layer is studied. The decreases of the nitride layer due to oxidation and trapping characteristics of interface state of multi layer dielectric film are investigated through the C-V measurement and F-N tunneling injection experiment using SONOS capacitor structure. Based on the experimental results, carrier trapping model for maximum flatband voltage shift of multi layer dielectric film is proposed and compared with experimental data. As a results of curve fitting, interface trap density between the top oxide and layer is determined as being $5{\times}10^11$~$2{\times}10^12$[$eV^1$$cm^2$].

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Effects of Vacuum Annealing on the Electrical Properties of Sputtered Vanadium Oxide Thin Films (스퍼터된 바나듐 산화막의 전기적 특성에 미치는 진공 어닐링의 효과)

  • Hwang, In-Soo;Lee, Seung-Chul;Choi, Bok-Gil;Choi, Chang-Kyu;Kim, Nam-Chul
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2003.11a
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    • pp.435-438
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    • 2003
  • The effects of oxygen partial pressure and vacuum annealing on the electrical properties of sputtered vanadium oxide($VO_x$) thin films were investigated. The thin films were prepared by r.f. magnetron sputtering from $V_2O_5$ target in a gas mixture of argon and oxygen. The oxygen/(oxygen+argon) partial pressure ratio of 0% and 8% is adopted. Electrical properties of films sputter-deposited under different oxygen gas pressures and in situ annealed in vacuum at $400^{\circ}C$ for 1h and 4h are characterized through electrical conductivity measurements. I-V characteristics were distinguished between linear and nonlinear region. In the low field region the conduction is due to Schottky emission, while at high fields it changes to Fowler-Nordheim tunneling type conduction. The conductivity measurements have shown an Arrhenius dependence of the conductivity on the temperature.

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Fabrication and Electrical Transport Characteristics of All-Perovskite Oxide DyMnO3/Nb-1.0 wt% Doped SrTiO3 Heterostructures

  • Wang, Wei Tian
    • Korean Journal of Materials Research
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    • v.30 no.7
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    • pp.333-337
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    • 2020
  • Orthorhombic DyMnO3 films are fabricated epitaxially on Nb-1.0 wt%-doped SrTiO3 single crystal substrates using pulsed laser deposition technique. The structure of the deposited DyMnO3 films is studied by X-ray diffraction, and the epitaxial relationship between the film and the substrate is determined. The electrical transport properties reveal the diodelike rectifying behaviors in the all-perovskite oxide junctions over a wide temperature range (100 ~ 340 K). The forward current is exponentially related to the forward bias voltage, and the extracted ideality factors show distinct transport mechanisms in high and low positive regions. The leakage current increases with increasing reverse bias voltage, and the breakdown voltage decreases with decrease temperature, a consequence of tunneling effects because the leakage current at low temperature is larger than that at high temperature. The determined built-in potentials are 0.37 V in the low bias region, and 0.11 V in the high bias region, respectively. The results show the importance of temperature and applied bias in determining the electrical transport characteristics of all-perovskite oxide heterostructures.

Hydrogen-Related Gate Oxide Degradation Investigated by High-Pressure Deuterium Annealing (고압 중수소 열처리 효과에 의해 조사된 수소 결합 관련 박막 게이트 산화막의 열화)

  • 이재성
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.41 no.11
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    • pp.7-13
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    • 2004
  • Experimental results are presented for the degradation of 3 nm-thick gate oxide under -2.5V $\leq$ V$_{g}$ $\leq$-4.0V stress and 10$0^{\circ}C$ conditions using P and NMOSFETs that are annealed with hydrogen or deuterium gas at high-pressure (5 atm). The degradation mechanisms are highly dependent on stress conditions. For low gate voltage, hole-trapping is found to dominate the reliability of gate oxide both in P and NMOSFETs. With increasing gate voltage to V$_{g}$ =-4.0V, the degradation becomes dominated by electron-trapping in NMOSFETs, however, the generation rate of "hot" hole was very low, because most of tunneling electrons experienced the phonon scattering before impact ionization at the Si interface. Statistical parameter variations as well as the gate leakage current depend on and are improved by high-pressure deuterium annealing, compared to corresponding hydrogen annealing. We therefore suggest that deuterium is effective in suppressing the generation of traps within the gate oxide. Our results therefore prove that hydrogen related processes are at the origin of the investigated oxide degradation.gradation.

Characteristics of Si Floating Gate Nonvolatile Memory Based on Schottky Barrier Tunneling Transistor (쇼트키 장벽 관통 트랜지스터 구조를 적용한 실리콘 나노점 부유 게이트 비휘발성 메모리 특성)

  • Son, Dae-Ho;Kim, Eun-Kyeom;Kim, Jeong-Ho;Lee, Kyung-Su;Yim, Tae-Kyung;An, Seung-Man;Won, Sung-Hwan;Sok, Jung-Hyun;Hong, Wan-Shick;Kim, Tae-You;Jang, Moon-Gyu;Park, Kyoung-Wan
    • Journal of the Korean Vacuum Society
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    • v.18 no.4
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    • pp.302-309
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    • 2009
  • We fabricated a Si nano floating gate memory with Schottky barrier tunneling transistor structure. The device was consisted of Schottky barriers of Er-silicide at source/drain and Si nanoclusters in the gate stack formed by LPCVD-digital gas feeding method. Transistor operations due to the Schottky barrier tunneling were observed under small gate bias < 2V. The nonvolatile memory properties were investigated by measuring the threshold voltage shift along the gate bias voltage and time. We obtained the 10/50 mseconds for write/erase times and the memory window of $\sim5V$ under ${\pm}20\;V$ write/erase voltages. However, the memory window decreased to 0.4V after 104seconds, which was attributed to the Er-related defects in the tunneling oxide layer. Good write/erase endurance was maintained until $10^3$ write/erase times. However, the threshold voltages moved upward, and the memory window became small after more write/erase operations. Defects in the LPCVD control oxide were discussed for the endurance results. The experimental results point to the possibility of a Si nano floating gate memory with Schottky barrier tunneling transistor structure for Si nanoscale nonvolatile memory device.