• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1085-1088
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• 2003

In this work, we fabricated a gas-sensing device based on porous silicon(PS), and its I-V and C-V properties were investigated for sensing alcohol vapor. The structure of the sensor consists of thin Au/Oxidized porous silicon/porous silicon/Silicon/Al, where the silicon substrate is etched anisotropically to be prepared into a membrane shape. As the result, I-V curves showed typical tunneling property, and C-V curves were shaped like those of a MIS (metal-insulator- semiconductor) capacitor, where the capacitance in accumulation was increased with alcohol vapor concentration.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.21 no.8
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• pp.699-705
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• 2008

Capacitance versus voltage (C-V) characteristics of Ge-nanocrystal (NC)-embedded metal-oxide-semiconductor (MOS) capacitors with $HfO_2$ gate material were investigated in this work. The current versus voltage (I-V) curves obtained from Ge-NC-embedded MOS capacitors fabricated with the $NH_3$ annealed $HfO_2$ gate material reveal the reduction of leakage current, compared with those of MOS capacitors fabricated with the $O_2$ annealed $HfO_2$ gate material. The C-V curves of the Ge-NC-embedded MOS capacitor with $HfO_2$ gate material annealed in $NH_3$ ambient exhibit counterclockwise hysteresis loop of about 3.45 V memory window when bias voltage was varied from -10 to + 10 V. The observed hysteresis loop indicates the presence of charge storages in the Ge NCs caused by the Fowler-Nordheim (F-N) tunneling. In addition, capacitance versus time characteristics of Ge-NC-embedded MOS capacitors with $HfO_2$ gate material were analyzed to investigate their retention property.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.3
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• pp.224-236
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• 2013

This work presents a comparative study of four Double Gate tunnel FET (DG-TFET) architectures: conventional p-i-n DG-TFET, p-n-p-n DG-TFET, a gate dielectric engineered Heterogate (HG) p-i-n DG-TFET and a new device architecture with the merits of both Hetero Gate and p-n-p-n, i.e. HG p-n-p-n DG-TFET. It has been shown that, the problem of high gate capacitance along with low ON current for a p-i-n TFET, which severely hampers the circuit performance of TFET can be overcome by using a p-n-p-n TFET with a dielectric engineered Hetero-gate architecture (i.e. HG p-n-p-n). P-n-p-n architecture improves the ON current and the heterogeneous dielectric helps in reducing the gate capacitance and suppressing the ambipolar behavior. Moreover, the HG architecture does not degrade the output characteristics, unlike the gate drain underlap architecture, and effectively reduces the gate capacitance.

• Journal of the Korean Magnetics Society
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• v.12 no.2
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• pp.68-72
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• 2002

In this research, the effects of capacitance to the access time were studied at the junction area of tunneling magnetoresistance when these were used as memory devices. These results were obtained by applying electric signal input and magnetic field was not used. We applied bipolar square waves of 1MHz to the MTJ samples to obtain the results and time constant ($\tau$) calculated by observing wave responses utilizing an oscilloscope. And time constant was compared with junction area. Each part of MTJ sample, such as electrical pad, lead and contact area, was modeled as an electrical equivalent circuit based on experimental results. For the 200㎛$\times$200㎛ cell, junction capacitance was 90 pF. Also, measurement and simulation results were compared, which showed those similarity.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.852-855
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• 2012

A DC-DC converter for EEPROM IPs which perfom erasing by the FN (Fowler-Nordheim) tunneling and programming by the band-to-band tunneling is designed in this paper. For the DC-DC converter for EEPROM IPs using a low voltage of $1.5V{\pm}10%$ as the logic voltage, a scheme of using VRD (Read Voltage) instead of VDD is proposed to reduce the pumping stages and pumping capacitances of its charge pump circuit. VRD ($=3.1V{\pm}0.1V$) is a regulated voltage by a voltage regulator using an external voltage of 5V. The designed DC-DC converter outputs VPP (=8V) and VNN (=-8V) in the write mode.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1997.04a
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• pp.318-322
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• 1997

The (Sr$_{l-x}$.Ca$_{x}$)TiO$_3$(0.05$\leq$x$\leq$0.2) ceramics were fabricated to form semiconducting ceramics by sintering at about 1350[$^{\circ}C$] in a reducing atmosphere($N_2$gas). After being fired in a reducing atmosphere, metal oxides, CuO, was painted on the both surface of the specimens to diffuse to the grain boundary. They were annealed at 1100[$^{\circ}C$] for 2 hours and cooled to room temperature. The grain boundary was composed of the continuous insulating layers. The capacitance changes slowly and almost linearly in the temperature region of -30~+85[$^{\circ}C$]. The capacitance characteristics appears a stable value within $\pm$10[%]. The conduction mechanism of the specimens observed in the temperature range of 25~125[$^{\circ}C$], and is divined into three regions haying different mechanism as the current increased: the region I below 230[V/cm] shows the ohmic conduction. The region II can be explained by the Poole-Frenkel emission theory, and the region III is dominated by the tunneling effect.ect.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.17 no.1
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• pp.21-26
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• 2004

Ultra-thin silicon dioxides were grown on p-type(100) oriented silicon employing rapid thermal dry oxidation technique at the temperature range of 850∼1050 $^{\circ}C$. The growth rate of the ultra-thin film was fitted well with tile model which was proposed recently by da Silva ＆ Stosic. The capacitance-voltage, current-voltage, characteristics were used to study the electrical properties of these thin oxides. The minimum interface state density around the midgap of the MOS capacitor having oxide thickness of 111.6 $\AA$ derived from the C-V curve was ranged from 6 to 10${\times}$10$^{10}$ /$\textrm{cm}^2$eV.

• Electrical & Electronic Materials
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• v.11 no.10
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• pp.94-99
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• 1998

Suitable replacement materials for ultrathin SiO2 in deeply scaled MOSFETs such as lattice polarizable films, which have much higherpermittivities than SiO2, have bandgaps of only 3.0 to 4.0 eV. Due to these small bandgaps, the reliability of these films as a gate insulator is a serious concern. Ramped voltage, time dependent dielectric breakdown, and hot carrier effect measurements were done on 190 layers of TiO2 which were deposited through the metal-organic chemical vapor deposition of titanium tetrakis-isopropoxide (TTIP). Measurements of the high and low frequency capacitance indicate that virtually no interface state are created during constant current injection stress. The increase in leakage upon electrical stress suggests that uncharged, near-interface states may be created in the TiO2 film near the SiO2 interfacial layer that allow a tunneling current component at low bias.

• Electrical & Electronic Materials
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• v.8 no.6
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• pp.752-758
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• 1995

Red emitting CaS:Eu,S electroluminescent(EL) device prepared at 550.deg. C by an electron-beam evaporation technique, demonstrated luminance of 175cd/m$\^$2/ and efficiency of 0.311m/W with 3kHz drive. Luminance was increased with the increase of applied voltage and frequency. From the results of the PL spectrum and the EL spectrum, the CaS:Eu, S device showed emission peak near 640nm resulted from the transition of EU$\^$2+/ 4f$\^$6/5d.rarw.4f$\^$7/. The capacitance of the phosphor layer from the Sawyer-Tower circuit was 10.5nF/cm$\^$2/.

• Journal of Electrical Engineering and Technology
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• v.9 no.2
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• pp.649-654
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• 2014

In this paper, an analytical model for Surrounding Gate (SG) metal-oxide- semiconductor field effect transistors (MOSFETs) considering quantum effects is presented. To achieve this goal, we have used variational approach for solving the Poission and Schrodinger equations. This model is developed to provide an analytical expression for inversion charge distribution function for all regions of device operation. This expression is used to calculate the other important parameters like inversion charge density, threshold voltage, drain current and gate capacitance. The calculated expressions for the above parameters are simple and accurate. This paper also focuses on the gate tunneling issue associated with high dielectric constant. The validity of this model was checked for the devices with different dimensions and bias voltages. The calculated results are compared with the simulation results and they show good agreement.