• ETRI Journal
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• v.35 no.3
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• pp.425-430
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• 2013

In this paper, we propose a triple-gate trench power MOSFET (TGRMOS) that is made through a modified RESURF stepped oxide (RSO) process, that is, the nitride_RSO process. The electrical characteristics of TGRMOSs, such as the blocking voltage ($BV_{DS}$) and on-state current ($I_{D,MAX}$), are strongly dependent on the gate configuration and its bias condition. In the nitride_RSO process, the thick single insulation layer ($SiO_2$) of a conventional RSO power MOSFET is changed to a multilayered insulator ($SiO_2/SiN_x/TEOS$). The inserted $SiN_x$ layer can create the selective etching of the TEOS layer between the gate oxide and poly-Si layers. After additional oxidation and the poly-Si filling processes, the gates are automatically separated into three parts. Moreover, to confirm the variation in the electrical properties of TGRMOSs, such as $BV_{DS}$ and $I_{D,MAX}$, simulation studies are performed on the function of the gate configurations and their bias conditions. $BV_{DS}$ and $I_{D,MAX}$ are controlled from 87 V to 152 V and from 0.14 mA to 0.24 mA at a 15-V gate voltage. This $I_{D,MAX}$ variation indicates the specific on-resistance modulation.

• Journal of IKEEE
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• v.9 no.2 s.17
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• pp.161-169
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• 2005

This paper presents the new structural Low voltage LVTSCR and TWSCR ESD protection circuit. The proposed ESD protection circuit has lower triggering voltage than conventional circuits. And the LVTSCR has the triggering voltage of 9V, current of 7mA and can pass below 0.8KV (150mA/um). The triggering voltage of the Triple-well SCR measured to 6V and the current is 40mA. By the substrate and gate bias, the triggering voltage is lowered down to $4{\sim}5.5V$.

• Journal of Electrical Engineering and Technology
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• v.9 no.4
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• pp.1355-1359
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• 2014

In the proposed work a 2D analytical modeling of single halo Triple material Surrounding Gate (SH-TMSG) MOSFET is developed. The Surface potential and Electric Field has been derived using parabolic approximation method and the simulation results are analyzed. The essential substantive is provided which elicits the deterioration of short channel effects and the results of the analytical model are delineated and compared with MEDICI simulation results and it is well corroborated.

• Transactions on Electrical and Electronic Materials
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• v.17 no.6
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• pp.329-334
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• 2016

In this work, the temperature dependence of electrical parameters of nanoscale SOI (silicon-on-insulator) TG (triple gate) n-FinFET (n-channel Fin field effect transistor) was investigated. Numerical device simulator $ATLAS^{TM}$ was used to construct, examine, and simulate the structure in three dimensions with different models. The drain current, transconductance, threshold voltage, subthreshold swing, leakage current, drain induced barrier lowering, and on/off current ratio were studied in various biasing configurations. The temperature dependence of the main electrical parameters of a SOI TG n-FinFET was analyzed and discussed. Increased temperature led to degraded performance of some basic parameters such as subthreshold swing, transconductance, on-current, and leakage current. These results might be useful for further development of devises to strongly down-scale the manufacturing process.

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07a
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• pp.342-344
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• 2005

We have simulated a symmetric dual-gate TFT which has triple floating n+ channel to improve the on-current of the dual-gate TFT. We achieved a low hole concentration at the source and channel junction causes the improvement the potential barrier so that we observed the reduction of the kink-effect. In this paper, we observed the reduction of the kink-effect compared with the conventional single-gate TFT and the improvement of the on-current compared with the conventional dual-gate TFT.

• The Journal of Dong Guk Oriental Medicine
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• v.2 no.1
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• pp.1-17
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• 1993

This study is to know the concept and function of Vital Gate. The results are summarized as follows, 1. Vital Gate is the original of life, which is essential to life. 2. A physiological function of Vital Gate controls the physiological activity of the whole body through Triple Heater. 3. It is said that a partial establishment of Vital Gate is the concept of Hwang Jeong(黃庭) as the central point of the body. 4. It is effective that a clinical application of Vital Gate uses on the basis of Zoagyuyeum(左歸飮) and Woogyuyeum(右歸陰). 5. Fire of the Vital Gate means a original activity of life-activity and is different from the concept of the fire of Pericardium as a substitute for King Fire. 6. It is said that to explain the essence of Vital Gate in relation of kidney is to say the generative function. According to the above results, Vital Gate is understood as the control of physiological activity of the whole body as the original point of life-activity.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08b
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• pp.1168-1171
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• 2007

Integrating systems on TFT-LCD panels is more and more popular for the mobile display application. However, it may not be necessary to use LTPS TFT devices. A-Si TFTs are used to integrate systems on TFT-LCD panels, especially scan (gate) drivers. To further reduce the chip size of driver IC, the triplegate pixel structure is developed. Therefore, the number of the source lines is reduced to 1/3 times.

• Journal of Mechanical Science and Technology
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• v.17 no.11
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• pp.1746-1755
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• 2003

Operating characteristics of a triple pressure reheat HRSG are analyzed using a commercial software package (Gate Cycle by GE Enter Software). The calculation routine determines all the design parameters including configuration and area of each heat exchanger. The off-design calculation part has the capability of simulating the effect of any operating parameters such as power load, process requirements, and operating mode, etc., on the transient performance of the plant. The arrangement of high-temperature and intermediate-temperature components of the HRSG is changed, and its effect on the steam turbine performance and HRSG characteristics is examined. It is shown that there could be a significant difference in HRSG sizes even though thermal performance is not in great deviation. From the viewpoint of both economics and steam turbine performance, it should be carefully reviewed whether the optimum design point could exist. Off-design performance could be one of the main factors in arranging components of the HRSG because power plants operate at various off-design conditions such as ambient temperature and gas turbine load, etc. It is shown that different heat exchanger configurations lead to different performances with ambient temperature, even though they have almost the same performances at design points.

• The Transactions of the Korean Institute of Power Electronics
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• v.25 no.5
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• pp.412-419
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• 2020

In this study, a 70 W buck converter using GaN metal-oxide-semiconductor field-effect transistor (MOSFET) is developed. This converter exhibits over 97 % efficiency, high power density, and 48 V-to-12 V/1.2 V/1 V (triple output). Three gate drivers and six GaN MOSFETs are placed in a 1 ㎠ area to enhance power density and heat dissipation capacity. The theoretical switching and conduction losses of the GaN MOSFETs are calculated. Inductances, capacitances, and resistances for the output filters of the three buck converters are determined to achieve the desired current, voltage ripples, and efficiency. An equivalent circuit model for the thermal analysis of the proposed triple-output buck converter is presented. The junction temperatures of the GaN MOSFETs are estimated using the thermal model. Circuit operation and temperature analysis are evaluated using a circuit simulation tool and the finite element analysis results. An experimental test bed is built to evaluate the proposed design. The estimated switch and heat sink temperatures coincide well with the measured results. The designed buck converter has 130 W/in³ power density and 97.6 % efficiency.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.351.1-351.1
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• 2014

In this study, we prepared the solution-based In-Ga-Zn oxide thin film transistors (IGZO TFTs) of multistacked active layer and characterized the gate bias instability by measuring the change in threshold voltage caused by stacking. The solutions for IGZO active layer were prepared by In:Zn=1:1 mole ratio and the ratio of Ga was changed from 20% to 30%. The TFTs with multistacked active layer was fabricated by stacking single, double and triple layers from the prepared solutions. As the number of active layer increases, the saturation mobility shows the value of 1.2, 0.8 and 0.6 (). The electrical properties have the tendency such as decreasing. However when gate bias VG=10 V is forced to gate electrode for 3000 s, the threshold voltage shift was decreased from 4.74 V to 1.27 V. Because the interface is formed between the each layers and this affected the current path to reduce the electrical performances. But the uniformity of active layer was improved by stacking active layer with filling the hole formed during pre-baking so the stability of device was improved. These results suggest that the deposition of multistacked active layer improve the stability of the device.