• Journal of the Korean Institute of Telematics and Electronics
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• v.18 no.5
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• pp.10-14
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• 1981

This paper deals with design of circuit that gives a linear relationship between the voltage controlling the Phase delay an인e of thrysistor trigger pulse and the average voltage in the load. The design is based an the method of linear triggering of thrysistion. It is shown that method is also effective with the input signal how variable frequencies.

• Journal of Power Electronics
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• v.17 no.6
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• pp.1650-1657
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• 2017

In this study, the distributed secondary voltage control of islanded microgrids with multi-agent consensus algorithm is investigated. As an alternative to a time-triggered approach, an event-triggered scheme is proposed to reduce the communication load among inverter-based distributed generators (DGs). The proposed aperiodic control scheme reduced unnecessary utilization of limited network bandwidth without degrading control performance. By properly establishing a distributed triggering condition in DG local controller, each inverter is only required to send voltage information when its own event occurs. The compensation of voltage amplitude deviation can be realized, and redundant data exchange related to fixed high sampling rate can be avoided. Therefore, an efficient use of communication infrastructure can be realized, particularly when the system is operating in steady state. The effectiveness of the proposed scheme is verified by simulations on a microgrid test system.

• Journal of IKEEE
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• v.11 no.1 s.20
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• pp.69-76
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• 2007

This paper presents the design of LVDS (Low-Voltage-Differential-Signaling) transmitter for Gb/s-per-pin operation. The proposed LVDS transmitter is designed using BiCMOS technology, which can be compatible with CMOS technology. To reduce chip area and enhance the robustness of LVDS transmitter, the MOS switches of transmitter are replaced with lateral bipolar transistor. The common emitter current gain($\beta$) of designed bipolar transistor is 20 and the cell size of LVDS transmitter is $0.01mm^2$. Also the proposed LVDS driver is operated at 1.8V and the maximum data rate is 2.8Gb/s approximately In addition, a novel ESD protection circuit is designed to protect the ESD phenomenon. This structure has low latch-up phenomenon by using turn on/off character of P-channel MOSFET and low triggering voltage by N-channel MOSFET in the SCR structure. The triggering voltage and holding voltage are simulated to 2.2V, 1.1V respectively.

• Journal of IKEEE
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• v.15 no.4
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• pp.330-338
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• 2011

In this paper, a current-mode buck-boost converter using Multiple switching devices is presented. The efficiency of the proposed converter is higher than that of conventional buck-boost converter. In order to improve the power efficiency at the high current level, the proposed converter is controlled with PWM(pulse width modulation) method. The converter has maximum output current 300mA, input voltage 3.3V, output voltage from 700mV to 12V, 1.5MHz oscillation frequency, and maximum efficiency 90%. Moreover, this paper proposes watchdog circuits in order to ensure the reliability and to improve the performance of dc-dc converters. An electrostatic discharge(ESD) protection circuit for deep submicron CMOS technology is presented. The proposed circuit has low triggering voltage using gate-substrate biasing techniques. Simulated result shows that the proposed ESD protection circuit has lower triggering voltage(4.1V) than that of conventional ggNMOS(8.2V).

• Journal of electromagnetic engineering and science
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• v.18 no.1
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• pp.20-28
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• 2018

The time synchronization of each sub-unit of a pulsed generator is important to generate an output high-power radio frequency (RF) signal. To obtain the time synchronization between an input RF signal fed by an external source and an electron beam produced by an electric pulse generator, the influence of different charging voltages on a delay and a rise time of the output pulse waveform in the electric pulse generator should be carefully considered. This paper aims to study the timing characteristics of the delay and the rise time as a function of different charging voltages with a peak value of less than -35 kV in the high-voltage pulse generator, including a trigger generator (TG) and a pulse-forming line (PFL). The simulation has been carried out to estimate characteristics in the time domain, in addition to their output high-voltage amplitude. Experimental results compared with those obtained by simulation indicate that the delay of the output pulses of the TG and PFL, which are made by controlling the external triggering signal with respect to different charging voltages, is getting longer as the charging voltage is increasing, and their rise times are inversely proportional to the amplitude of the charging voltage.

• 전기의세계
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• v.23 no.4
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• pp.60-65
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• 1974

This paper is to study on the pilot work of bi-directional S.C.R. power converter adopted by the method of diode-bridge type circuit. This apparatus acts as a converter when it is used in convering 3-phase a.c source to d.c output, and it can be used as an inverter which recovering surplus d.c power to a.c source when d.c load become active to cause the induced voltage higher than the presetted point of d.c output voltage. At the same time, its d.c voltage varies continuously in the presetted range of positive and/or negative polarity. As a result of test, the AC/DC bi-directional power converter represents maximum converting efficiency of 91% and power factor of 0.98. Furthermore, this converter also can be applied as a cycleconverter by varying the period of gate triggering signal.

• Journal of IKEEE
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• v.21 no.2
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• pp.150-153
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• 2017

In this paper, a structure of GCNMOS based ESD protection circuit using floating-body technique is proposed. TCAD simulation of Synopsys was used to compare with the conventional GGNMOS and GCNMOS. Compared with the conventional GCNMOS, the proposed ESD protection circuit has lower trigger voltage and faster turn-on-time than conventional circuit because of the added NMOSFET. In the simulation result, the triggering voltage of the proposed ESD protection circuit is 4.86V and the turn-on-time is 1.47ns.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.4
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• pp.42-50
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• 2003

This paper presents an embedded RC oscillator which has temperature compensation circuits. The conventional RC oscillator has frequency deviation about 15%, which is caused by variation of resistors and the reference voltage of schmitt trigger from the temperature condition. In this paper, the proposed circuit use a CMOS bandgap reference having balanced current temperature coefficients as a triggering voltage of schmitt trigger. The constant current sources consist of current mirror circuit with the positive and negative temperature coefficient. The proposed circuit shows less 3% frequency deviation for variation of temperature, supply voltage and process parameters.

• Proceedings of the KIEE Conference
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• 1999.07e
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• pp.2173-2175
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• 1999

This paper presents the development of closing switch for high voltage and current in detail. Design concept of INPIStron triggered by the gas puffing, voltage hold-off, current capacity, insulating and electrode material, rise time etc, are described. Also for the dptimized design of the electrical triggering switch, pin, ring, wire brush, surface discharge and HCP(Hypo-Cycloidal Pinch) trigger are considered.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.6
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• pp.797-801
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• 2014

This research presented the concept of employing the punch-through diode triggered SCRs (PTTSCR) for low voltage ESD applications such as transient voltage suppression (TVS) devices. In order to demonstrate the better electrical properties, various traditional ESD protection devices, including a silicon controlled rectifier (SCR) and Zener diode, were simulated and analyzed by using the TCAD simulation software. The simulation result demonstrates that the novel PTTSCR device has better performance in responding to ESD properties, including DC dynamic resistance and capacitance, compared to SCR and Zener diode. Furthermore, the proposed PTTSCR device has a low reverse leakage current that is below $10^{-12}$ A, a low capacitance of $0.07fF/mm^2$, and low triggering voltage of 8.5 V at $5.6{\times}10^{-5}$ A. The typical properties couple with the holding voltage of 4.8 V, while the novel PTTSCR device is compatible for protecting the low voltage, high speed ESD protection applications. It proves to be good candidates as ultra-low capacitance TVS devices.