• Title/Summary/Keyword: transmission line pulse

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Measurement of Time Delay in Optical Fiber Line Using Rayleigh Scattering (Rayleigh 산란을 이용한 광선로의 time delay 측정)

  • Kwon, Hyung-Woo;Yu, Il;Yu, Yun-Sik
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.37 no.5B
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    • pp.365-369
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    • 2012
  • It is very important to control synchronization by inter-network delay compensation in high speed synchronous optcial transmission network systems. In this study we designed a delay measurement system based on OTDR using Rayleigh backscatterer in order to compensate for time delay due to the length of optical fiber line. We observed waveform variations on both averaging time and peak power of laser pulse. Finally, we executed experimental demonstration on its accuracy and test repeatability by comparison to the methods practically used in the industry. Experimental results show maximum error of 0.06usec and standard deviation of 0.021usec, which means it's possibly applied to delay control system for mobile repeaters and stations.

Transmit-receive Module for Ka-band Seekers using Multi-layered Liquid Crystal Polymer Substrates (다층 액정폴리머 기판을 이용한 Ka대역 탐색기용 송수신 모듈)

  • Choi, Sehwan;Ryu, Jongin;Lee, Jaeyoung;Lee, Jiyeon;Nam, ByungChang
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.20 no.5
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    • pp.63-70
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    • 2020
  • In this paper, the transmit-receive module for military seekers has been designed and fabricated in 35 GHz. To increase the performance of substrates and high integration of circuits in millimeter-wave band, a 4-layer LCP(Liquid Crystal Polymer) substrate was developed. This substrate was implemented with three FCCL substrates and two adhesive layers, and a process using the difference in melting point between the substrates was used for lamination. Using a strip line and a microstrip line was confirmed by the transmission loss along the length of the substrate, and the performance of LCP substrates was validated with a power divider in 35 GHz. After confirming the performance of individual blocks such as power amplifier and low noise amplifier, a single channel Ka-band transmission/reception module was developed using a 4-layer liquid crystal polymer substrate. The transmit power of this module has above 1.1W in pulse duty 10% and has an output power of 1.1W and it has receive noise figure less than 8.5 dB and receive gain more than 17.6 dB.

Pump Light Power of Wideband Optical Phase Conjugator using HNL-DSF in WDM Systems with MSSI (MSSI 기법을 채택한 WDM 시스템에서 HNL-DSF를 이용한 광대역 광 위상 공액기의 펌프 광 전력)

  • Lee Seong real;Cho Sung eun
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.30 no.3A
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    • pp.168-177
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    • 2005
  • In this paper, we numerically investigated the optimum pump light power resulting best compensation of pulse distortion due to both chromatic dispersion and self phase modulation (SPM) in long-haul 3×40 Gbps wavelength division multiplexing (WDM) systems. We used mid-span spectral inversion (MSSI) method with path-averaged intensity approximation (PAIA) as compensation approach, which have highly nonlinear dispersion shifted fiber (HNL-DSF) as nonlinear medium of optical phase conjugator (OPC) in the mid-way of total transmission line. We confirmed that HNL-DSF is an useful nonlinear medium in OPC for wideband WDM transmission, and in order to achieve the excellent compensation the pump light power is selected to equal the conjugated light power into the latter half fiber section with the input light power of WDM channel depending on total transmission length. Also we confirmed that compensation degree of WDM channel with small conversion efficiency is improved by using pump light power increasing power conversion ratio upper than 1.

Several systems for 1Giga bit Modem

  • Park, Jin-Sung;Kang, Seong-Ho;Eom, Ki-Whan;Sosuke, Onodera;Yoichi, Sato
    • 제어로봇시스템학회:학술대회논문집
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    • 2003.10a
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    • pp.1749-1753
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    • 2003
  • We proposed several systems for 1Giga bit Modem. The first, Binary ASK(Amplitude Shift Keying) system has a high speed shutter transmitter and no IF(Intermediate Frequency) receiver only by symbol synchronization. The advantage of proposed system is that circuitry is very simple without IF process. The disadvantage of proposed system are that line spectrum occurs interference to other channels, and enhancement to 4-level system is impossible due to its large SNR degradation. The second, Binary phase modulation system has a high speed shutter transmitter and IF-VCO(IF-Voltage Controlled Oscillator) control by base-band phase rotation. Polarity of shutter window is changed by the binary data. The window should be narrow same as above ASK. The advantage of proposed system is which error rate performance is superior. The disadvantage of proposed system are that Circuitry is more complex, narrow pull-in range of receiver caused by VCO and spectrum divergence by the non-linear amplifier. The third, 4-QAM(Quadrature Amplitude Modulation)system has a nyquist pulse transmitter and IF-VCO control by symbol clock. The advantage of proposed system are that signal frequency band is a half of 1GHz, reliable pull-in of VCO and possibility of double speed transmission(2Gbps) by keeping 1GHz frequency-band. The disadvantage of proposed system are that circuit complexity of pulse shaping and spectrum divergence by the non-linear amplifier.

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Design of a Bounded-wave EMP Simulator Antenna (Bounded-wave EMP Simulator 안테나의 설계)

  • Sun, Da-Young;Choi, Hak-Keun;Lim, Seong-Bin;Jang, Jae-Woong;Kim, Tae-Yoon;Choi, Geun-Kyung
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.11 no.5
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    • pp.87-93
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    • 2011
  • A threat of the EMP(Electromagnetic Pulse) is recently increasing, so the development of electromagnetic security technology against the EMP is needed. However, the state of the domestic electromagnetic security technology against the EMP is lower level than the foreign. In this paper, the bounded-wave EMP simulator antenna for the development of electromagnetic security technology against a threat of the EMP is designed. The structure of the designed antenna is from a sort of the basic form of the bounded-wave EMP simulator such as a parallel-plate simulator for testing EMP immunity performance within the EUT(Equipment Under Test). The design processes of the designed simulator is including wave launcher, transmission line and termination taper. In the working volume of the designed antenna, the test object within 30 cm is forming predominant TEM field, so it is confirmed that the designed EMP simulator antenna can be used as the EMP simulator.

Effects of Electrostatic Discharge Stress on Current-Voltage and Reverse Recovery Time of Fast Power Diode

  • Bouangeune, Daoheung;Choi, Sang-Sik;Cho, Deok-Ho;Shim, Kyu-Hwan;Chang, Sung-Yong;Leem, See-Jong;Choi, Chel-Jong
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.14 no.4
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    • pp.495-502
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    • 2014
  • Fast recovery diodes (FRDs) were developed using the $p^{{+}{+}}/n^-/n^{{+}{+}}$ epitaxial layers grown by low temperature epitaxy technology. We investigated the effect of electrostatic discharge (ESD) stresses on their electrical and switching properties using current-voltage (I-V) and reverse recovery time analyses. The FRDs presented a high breakdown voltage, >450 V, and a low reverse leakage current, < $10^{-9}$ A. From the temperature dependence of thermal activation energy, the reverse leakage current was dominated by thermal generation-recombination and diffusion, respectively, at low and high temperature regions. By virtue of the abrupt junction and the Pt drive-in for the controlling of carrier lifetime, the soft reverse recovery behavior could be obtained along with a well-controlled reverse recovery time of 21.12 ns. The FRDs exhibited excellent ESD robustness with negligible degradations in the I-V and the reverse recovery characteristics up to ${\pm}5.5$ kV of HBM and ${\pm}3.5$ kV of IEC61000-4-2 shocks. Likewise, transmission line pulse (TLP) analysis reveals that the FRDs can handle the maximum peak pulse current, $I_{pp,max}$, up to 30 A in the forward mode and down to - 24 A in the reverse mode. The robust ESD property can improve the long term reliability of various power applications such as automobile and switching mode power supply.

Highly Robust AHHVSCR-Based ESD Protection Circuit

  • Song, Bo Bae;Koo, Yong Seo
    • ETRI Journal
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    • v.38 no.2
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    • pp.272-279
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    • 2016
  • In this paper, a new structure for an advanced high holding voltage silicon controlled rectifier (AHHVSCR) is proposed. The proposed new structure specifically for an AHHVSCR-based electrostatic discharge (ESD) protection circuit can protect integrated circuits from ESD stress. The new structure involves the insertion of a PMOS into an AHHVSCR so as to prevent a state of latch-up from occurring due to a low holding voltage. We use a TACD simulation to conduct a comparative analysis of three types of circuit - (i) an AHHVSCR-based ESD protection circuit having the proposed new structure (that is, a PMOS inserted into the AHHVSCR), (ii) a standard AHHVSCR-based ESD protection circuit, and (iii) a standard HHVSCR-based ESD protection circuit. A circuit having the proposed new structure is fabricated using $0.18{\mu}m$ Bipolar-CMOS-DMOS technology. The fabricated circuit is also evaluated using Transmission-Line Pulse measurements to confirm its electrical characteristics, and human-body model and machine model tests are used to confirm its robustness. The fabricated circuit has a holding voltage of 18.78 V and a second breakdown current of more than 8 A.

Cathode Side Engineering to Raise Holding Voltage of SCR in a 0.5-㎛ 24 V CDMOS Process

  • Wang, Yang;Jin, Xiangliang;Zhou, Acheng;Yang, Liu
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.15 no.6
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    • pp.601-607
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    • 2015
  • A set of novel silicon controlled rectifier (SCR) devices' characteristics have been analyzed and verified under the electrostatic discharge (ESD) stress. A ring-shaped diffusion was added to their anode or cathode in order to improve the holding voltage (Vh) of SCR structure by creating new current discharging path and decreasing the emitter injection efficiency (${\gamma}$) of parasitic Bipolar Junction Transistor (BJT). ESD current density distribution imitated by 2-dimensional (2D) TCAD simulation demonstrated that an additional current path exists in the proposed SCR. All the related devices were investigated and characterized based on transmission line pulse (TLP) test system in a standard $0.5-{\mu}m$ 24 V CDMOS process. The proposed SCR devices with ring-shaped anode (RASCR) and ring-shaped cathode (RCSCR) own higher Vh than that of Simple SCR (S_SCR). Especially, the Vh of RCSCR has been raised above 33 V. What's more, their holding current is kept over 800 mA, which makes it possible to design power clamp with SCR structure for on chip ESD protection and keep the protected chip away from latch-up risk.

Improvement of ESD (Electrostatic Discharge) Protection Performance of NEDSCR (N-Type Extended Drain Silicon Controlled Rectifier) Device using CPS (Counter Pocket Source) Ion Implantation (CPS 이온주입을 통한 NEDSCR 소자의 정전기 보호 성능 개선)

  • Yang, Jun-Won;Seo, Yong-Jin
    • Journal of Satellite, Information and Communications
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    • v.8 no.1
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    • pp.45-53
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    • 2013
  • An electrostatic discharge (ESD) protection device, so called, N-type extended drain silicon controlled rectifier (NEDSCR) device, was analyzed for high voltage I/O applications. A conventional NEDSCR device shows typical SCR-like characteristics with extremely low snapback holding voltage. This may cause latch-up problem during normal operation. However, a modified NEDSCR device with proper junction/channel engineering using counter pocket source (CPS) ion implantation demonstrates itself with both the excellent ESD protection performance and the high latch-up immunity. Since the CPS implant technique does not change avalanche breakdown voltage, this methodology does not reduce available operation voltage and is applicable regardless of the operation voltage.

Shear Wave Velocity in Unconsolidated Marine Sediments of the Western Continental Margin, the East Sea

  • Kim, Gil-Young;Kim, Dae-Choul
    • The Journal of the Acoustical Society of Korea
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    • v.22 no.4E
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    • pp.167-175
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    • 2003
  • Shear wave velocity was measured and grain size analysis was conducted on two core samples obtained in unconsolidated marine sediments of the western continental margin, the East Sea. A pulse transmission technique based on the Hamilton frame was used to measure shear wave velocity. Duomorph ceramic bender transducer-receiver elements were used to generate and detect shear waves in sediment samples. Time delay was calculated by changing the sample length from the transducer-receiver element. Time delay is 43.18 μs and shear wave velocity (22.49 m/s) is calculated from the slope of regression line. Shear wave velocities of station 1 and 2 range from 8.9 to 19.0 m/s and from 8.8 to 22 mis, respectively. Shear wave velocities with depth in both cores are qualitatively in agreement with the compared model〔1〕, although the absolute value is different. The sediment type of two core samples is mud (mean grain size, 8-9Φ). Shear wave velocity generally increases with sediment depth, which is suggesting normally consolidated sediments. The complicated variation of velocity anisotropy with depth at station 2 is probably responsible for sediment disturbance by possible gas effect.